Mass storage data protection system for a gaming machine
A mass storage data protection system for use with a mass storage device in a gaming machine to protect the mass storage device from unauthorized commands. The mass storage data protection system includes a mass storage device command latch, a timing circuit for timing signals between the mass storage device command latch and the mass storage device, a comparator and a comparator command register in communication with the comparator. The comparator command register includes commands that generate a fault within the mass storage data protection system such that when the comparator receives a command from the mass storage device command latch corresponding to the command within the comparator command register, a fault is generated within the mass storage command latch.
1. A mass storage data protection system for use with a mass storage device in a gaming machine, the mass storage data protection system comprising:
a mass storage device command latch for storing commands from a disk controller;
a timing circuit for timing signals between the mass storage device command latch and the mass storage device;
a comparator between the mass storage device command latch and the timing circuit; and
a comparator command register in communication with the comparator, the comparator command register including ATA write commands wherein the comparator issues a fault when the mass storage device command latch stores a command matching an ATA command from the comparator command register.
2. A mass storage data protection system in accordance with claim 1 further comprising a control and status register in communication with the comparator command register and the comparator wherein the control and status register is configured to receive information from the comparator and to send information to the comparator command register and is operable to receive information from a jumper for enabling writing to the mass storage device.
3. A mass storage data protection system in accordance with claim 1 wherein the timing circuit comprises a synchronizer and a reset generator.
4. A mass storage data protection system in accordance with claim 1 wherein the mass storage device consists of an intelligent drive electronics hard disk drive and the mass storage device command latch consists of an intelligent drive electronics command latch.
5. A mass storage data protection system in accordance with claim 1 where in the comparator command register comprises a fixed command array and a user command array.
6. A mass storage data protection system for use with an intelligent drive electronics mass storage device in a gaming machine, the mass storage data protection system comprising:
an intelligent drive electronics mass storage device command latch for storing commands from a disk controller;
a timing circuit for timing signals between the intelligent drive electronics command latch and the intelligent drive electronics mass storage device, the timing circuit comprising a synchronizer and a reset generator;
a comparator comprising a fixed command array and a user command array, the comparator being located between the intelligent drive electronics command latch and the timing circuit;
a comparator command register in communication with the comparator, the comparator command register including ATA write commands; and
a control and stains register in communication with the comparator command register and the comparator, wherein the control and status resister is configured to receive information from the comparator and to send information to the comparator command register and is operable to receive information from a jumper for enabling writing to the mass storage device and; wherein the comparator issues a fault when the intelligent drive electronics mass storage device command latch stores a command matching an ATA command from the comparator command register.
7. A gaming machine comprising:
a housing; at least one user input coupled to the housing,
a display coupled to the housing;
and a control system, the control system comprising:
a mass storage device; and
a mass storage data protection system, the mass storage data protection system comprising:
a mass storage device command latch for storing commands from a disk controller;
a timing circuit for timing signals between the mass storage device command latch and the mass storage device;
a comparator between the mass storage device command latch and the timing circuit; and
a comparator command register in communication with the comparator, the comparator command register including ATA write commands wherein the comparator issues a fault when the mass storage device command latch stores a command matching an ATA command from the comparator command resister.
8. A gaming machine in accordance with claim 7 further comprising a control and status register in communication with the comparator command register and the comparator, wherein the control and status register is configured to receive information from the comparator and to send information to the comparator command register and is operable to receive information from a jumper for enabling writing to the mass storage device.
9. A gaming in accordance with claim 7 wherein the timing circuit comprises a synchronizer and a reset generator.
10. A gaming machine in accordance with claim 7 wherein the mass storage device consists of an intelligent drive electronics hard disk drive and the mass storage device command latch consists of an intelligent drive electronics command latch.
11. A gaming machine in accordance with claim 7 wherein the comparator command register comprises a fixed command array and a user command any.
12. A gaming machine comprising:
a housing; at least one user input coupled to the housing;
a display coupled to the housing; and
a control system, the control system comprising:
an intelligent drive electronics mass storage device; and
a mass storage data protection system, the mass data protection system comprising:
an intelligent drive electronics mass storage device command latch for storing commands from a disk controller;
a timing circuit for timing signals between the intelligent drive electronics command latch and the intelligent drive electronics mass storage device, the timing circuit comprising a synchronizer and a reset generator;
a comparator comprising a fixed command array and a user command array, the comparator being located between the intelligent drive electronics command latch and the timing circuit wherein the comparator issues a fault when the intelligent drive electronics mass storage device command latch stores a command matching an ATA command from a comparator command resister;
the comparator command register in communication with the comparator, the comparator command register including ATA write commands; and
a control and status register in communication with the comparator command register and the comparator, the control and status register wherein the control and status register is configured to receive information from the comparator and to send information to the comparator command register and is operable to receive information from a jumper or a write enable switch for enabling writing to the mass storage device.
13. A gaming machine in accordance with claim 12 wherein the control system further comprises: the write enable switch in communication with the comparator, the write enable switch being configured to suppress generation of a fault within the mass storage command latch when the write enable switch is close.
14. A gaming machine in accordance with claim 13 , farther comprising: a microprocessor in communication with the mass storage device and the mass storage data protection system; and gaming machine operating software running on the microprocessor, the gaming machine operating software having at least a gaming mode and a maintenance mode, wherein the gaming machine operating software is configured to suspend gaming operation when the write enable switch is closed and the gaming machine operating software is in a mode other than the maintenance mode.