Low-complexity, high accuracy model of a CPU power distribution system
View Patent ↗A low-complexity, high accuracy model of a CPU power distribution system has been developed. The model includes models of multiple power converters that input to a board model. The board model then inputs to a package model. Finally, the package model inputs to a chip model. The model provides a high degree of accuracy with an acceptable simulation time.
1. An apparatus for modeling a power system of a microprocessor based system, comprising:
a plurality of power converter models;
a board model that receives an output from the plurality of power converter models;
a package model that receives an output from the board model; and
a chip model that receives an output from the package model, wherein the chip model further comprises:
a plurality of bump and grid models;
a plurality of section models that receives a plurality of outputs from the plurality of bump and grid models, wherein each of the plurality of section models further comprises a load model; and
a plurality of channel models that interconnect the plurality of section models.
2. The apparatus of claim 1 , wherein the plurality of power converter models comprises a plurality of DC to DC power converter models.
3. The apparatus of claim 1 , wherein the plurality of power converter models comprises four DC to DC power converter models.
4. The apparatus of claim 1 , wherein the plurality of bump and grid models comprises nine bump and grid models.
5. The apparatus of claim 1 , wherein the load model comprises a voltage controlled resistor.
6. The apparatus of claim 1 , wherein the load model comprises a current source.
7. The apparatus of claim 1 , wherein the plurality of section models are arranged in an interconnecting grid.
8. The apparatus of claim 7 , wherein the interconnecting grid is generally square shaped.
9. The apparatus of claim 1 , wherein the plurality of section models comprises nine section models.
10. The apparatus of claim 9 , wherein the plurality of the section models are arranged in a three section by three section grid.
11. The apparatus of claim 1 , wherein the plurality of the channel models comprises ten section models.
12. An apparatus for modeling a power system of a microprocessor based system, comprising:
means for modeling a power converter;
means for modeling a board that receives an output from the means for modeling a power converter;
means for modeling a package that receives an output from the means for modeling a board; and
means for modeling a chip that receives an output from the means for modeling a package, wherein the means for modeling a chip further comprises:
means for modeling a plurality of bumps and grids;
means for modeling a plurality of sections that receive a plurality of outputs from the plurality of bumps and grids, wherein each of the plurality of sections further comprises a load model; and
means for modeling a plurality of channel models that interconnect the plurality of sections.
13. A method for modeling a power system of a microprocessor based system, comprising:
modeling a plurality of power converters;
modeling a board that receives an output from the plurality of power converter;
modeling a package that receives an output from the board; and
modeling a chip that receives an output from the package, wherein modeling a chip further comprises:
modeling a plurality of bump and grid components;
modeling a plurality of chip sections that receives an output from the plurality of bump and arid components, wherein modeling a plurality of chip sections further comprises modeling a load; and
modeling a plurality chip channels that interconnects the plurality of chip sections.
14. The method of claim 13 , wherein the plurality of power converters comprises four DC to DC power converters.
15. The method of claim 13 , wherein modeling a plurality of chip sections forms a generally square shaped grid.
16. The method of claim 15 , wherein the generally square shaped grid comprises a three section by three section grid.
17. The method of claim 13 , wherein the load is modeled as a voltage controlled resistor.
18. The method of claim 13 , wherein the load is modeled as a current source.
19. An apparatus for modeling a power system of a microprocessor chip, comprising:
a plurality of bump and grid models;
a plurality of section models that receives a plurality of outputs from the plurality of bump and grid models, wherein the plurality of section models further comprises a load model; and
a plurality of channel models that interconnect the plurality of section models.
20. The apparatus of claim 19 , wherein the load model further comprises a voltage controlled resistor.
21. The apparatus of claim 19 , wherein the load model further comprises a current source.
22. The apparatus of claim 19 , wherein the plurality of section models are arranged in an interconnecting grid.
23. The apparatus of claim 22 , wherein the interconnecting grid in generally square shaped.
24. The apparatus of claim 19 , wherein the plurality of section models comprises nine section models.
25. The apparatus of claim 24 , wherein the plurality of section models are arranged in a three section by three section grid.
26. An apparatus for modeling a power system of a microprocessor chip, comprising:
means for modeling a plurality of bumps and grids;
means for modeling a plurality of sections that receives a plurality of outputs from the plurality of bumps and grids, wherein means for modeling a plurality of sections further comprises means for modeling a load; and
means for modeling a plurality of channels that interconnect the plurality of sections.
27. A method for modeling a power system of a microprocessor chip, comprising:
modeling a plurality of bump and grid components;
modeling a plurality of chip sections that receives an output from the plurality of bump and grid components, wherein modeling a plurality of chip sections further comprises modeling a load; and
modeling a plurality chip channels that interconnect the plurality of chip sections.
28. The method of claim 27 , wherein modeling a plurality of chip sections forms a generally square shaped grid.
29. The method of claim 28 , wherein the generally square shaped grid is a three section by three section grid.
30. The method of claim 27 , wherein the load is modeled as a voltage controlled resistor.
31. The method of claim 27 , wherein the load is modeled as a current source.