IP Library Granted Patent US 7,028,119
Granted Patent B2
US 7,028,119 · App. 09/825,815 · Granted Apr 11, 2006

Automated tool for detection of potential race condition

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Quick Facts
Patent No.
US 7,028,119
App. No.
09/825,815
Granted
Apr 11, 2006
Kind
B2
Abstract

A method for detecting a potential race condition is provided comprising the steps of identifying a memory access in a source code segment, the source code segment being executable in any one of a plurality of execution threads; searching backward from the memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identifying the potential race condition if the assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and searching forward from the memory access through each of the plurality of threads for the deassert protection declaration, and identifying the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

Claims (64)

1. A method for detecting a potential race condition comprising the steps of:

identifying a memory access in a source code segment, the source code segment being executable in any one of a plurality of execution threads;

searching backward from the memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identifying the potential race condition if the assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and

searching forward from the memory access through each of the plurality of threads for the deassert protection declaration, and identifying the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

2. The method as recited in claim 1 wherein the step of identifying the memory access further comprises searching the source code segment for a static variable, the static variable being used to identify the memory access.

3. The method as recited in claim 1 wherein the step of identifying the memory access further includes searching the source code segment for a heap variable, the heap variable being used to identify the memory access.

4. The method as recited in claim 1 wherein the step of identifying the memory access further includes prompting a user for the memory access to identify.

5. The method as recited in claim 1 further including the step of identifying a type of protection declaration, and wherein the assert protection declaration is an assert protection declaration of the identified type, and wherein the deassert protection declaration is a deassert protection declaration of the identified type.

6. The method of claim 5 , wherein the type of protection declaration is one of an interrupt lock, a task lock, and a semaphore.

7. The method of claim 5 , wherein the type of protection declaration is one of an interrupt lock, a task lock, a mutex, and a semaphore.

8. The method as recited in claim 1 wherein the assert protection declaration is an interrupt lock and the deassert protection declaration is an interrupt unlock.

9. The method as recited in claim 1 wherein the assert protection declaration is a task lock and the deassert protection declaration is an task unlock.

10. The method as recited in claim 1 wherein the assert protection declaration is a take semaphore and the deassert protection declaration is a give semaphore.

11. The method as recited in claim 1 , wherein the searching steps further include the step of stopping the search when a maximum depth has been reached in the plurality of threads.

12. The method as recited in claim 1 wherein the steps of searching are performed recursively.

13. The method as recited in claim 1 wherein the step of searching backward is conducted in parallel on a plurality of processing devices.

14. The method as recited in claim 1 wherein the step of searching forward is conducted in parallel on a plurality of processing devices.

15. The method as recited in claim 1 wherein the steps of searching backward and forward are conducted in parallel on a plurality of processing devices.

16. A method for detecting a potential race condition comprising the steps of:

selecting one or more source code segments, the source code segments being executable in any one of a plurality of execution threads;

selecting a memory access to identify from the selected source code segments;

identifying the memory access in one or more of the selected source code segments;

searching backward from each memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identifying the potential race condition if the assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and

searching forward from each memory access through each of the plurality of threads for the deassert protection declaration, and identifying the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

17. The method as recited in claim 16 wherein the step of selecting the memory access further includes searching the source code segments for static variables, the static variables being used to identify the memory access.

18. The method as recited in claim 16 wherein the step of selecting the memory access further includes searching the source code segments for heap variables, the heap variables being used to identify the memory access.

19. The method as recited in claim 16 wherein the step of selecting the memory access further includes prompting a user for the memory access to identify.

20. The method as recited in claim 16 further including the step of identifying a type of protection declaration, and wherein the assert protection declaration is an assert protection declaration of the identified type, and wherein the deassert protection declaration is a deassert protection declaration of the identified type.

21. The method of claim 20 , wherein the type of protection declaration is one of an interrupt lock, a task lock, and a semaphore.

22. The method of claim 20 , wherein the type of protection declaration is one of an interrupt lock, a task lock, a mutex, and a semaphore.

23. The method as recited in claim 16 wherein the assert protection declaration is an interrupt lock and the deassert protection declaration is an interrupt unlock.

24. The method as recited in claim 16 wherein the assert protection declaration is a task lock and the deassert protection declaration is an task unlock.

25. The method as recited in claim 16 wherein the assert protection declaration is a take semaphore and the deassert protection declaration is a give semaphore.

26. The method as recited in claim 16 , wherein the searching steps further include the step of stopping the search when a maximum depth has been reached in the plurality of threads.

27. A computer readable medium, having stored thereon, computer executable process steps operative to control a computer to detect possible race conditions, the process steps comprising:

identifying a memory access in a source code segment, the source code segment being executable in any one of a plurality of execution threads;

searching backward from the memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identifying the potential race condition if the assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and

searching forward from the memory access through each of the plurality of threads for the deassert protection declaration, and identifying the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

28. A computer readable medium, having stored thereon, computer executable process steps operative to control a computer to detect possible race conditions, the process steps comprising:

selecting one or more source code segments, the source code segments being executable in any one of a plurality of execution threads;

selecting a memory access to identify from the selected source code segments;

identifying the memory access in one or more of the selected source code segments;

searching backward from each memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identifying the potential race condition if an assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and

searching forward from each memory access through each of the plurality of threads for the deassert protection declaration, and identifying the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

29. A system comprising:

a processing device coupled to a memory, the processing device operable to:

identify a memory access in a source code segment, the source code segment being executable in any one of a plurality of execution threads;

search backward from the memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identify the potential race condition if the assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and

search forward from the memory access through each of the plurality of threads for the deassert protection declaration, and identify the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

30. The system as recited in claim 29 wherein the processing device comprises a plurality of processors operating in parallel.

31. The system as recited in claim 30 wherein the memory further comprises a plurality of interconnected memory devices.

32. The system as recited in claim 29 wherein the memory comprises a plurality of interconnected memory devices.

33. A system comprising:

a processing device coupled to a memory, the processing device operative to:

select one or more source code segments, the source code segments being executable in any one of a plurality of execution threads;

select a memory access to identify from the selected source code segments;

identify the memory access in one or more of the selected source code segments;

search backward from each memory access through each of the plurality of threads for an assert protection declaration without any intervening deassert protection declaration, and identify the potential race condition if an assert protection declaration without any intervening deassert protection declaration was not found in each of the plurality of threads; and

search forward from each memory access through each of the plurality of threads for the deassert protection declaration, and identify the potential race condition if the deassert protection declaration was not found in each of the plurality of threads.

34. The system as recited in claim 33 wherein the processing device comprises a plurality of processors operating in parallel.

35. The system as recited in claim 34 wherein the memory further comprises a plurality of interconnected memory devices.

36. The system as recited in claim 33 wherein the memory comprises a plurality of interconnected memory devices.

37. The system as recited in claim 33 , wherein the processing device includes a plurality of processing devices and wherein at least two of the plurality of threads are searched backward in parallel on different ones of the plurality of processing devices.

38. The system as recited in claim 33 wherein the processing device includes a plurality of processing devices and wherein at least two of the plurality of threads are searched forward in parallel on different ones of the plurality of processing devices.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Dec 28, 2022
From: GUGGENHEIM CORPORATE FUNDING, LLC
To: WIND RIVER SYSTEMS, INC.
Reel/Frame 062239/0590 →
PATENT SECURITY AGREEMENT Recorded Dec 24, 2018
From: WIND RIVER SYSTEMS, INC.
To: GUGGENHEIM CORPORATE FUNDING, LLC
Reel/Frame 049148/0001 →