Method of reducing flickering and inhomogeneous brightness in LCD
View Patent ↗A method of reducing flickering and inhomogeneous brightness in an LCD. The method serially connects each scan line connecting a plurality of pixels in a row with a resistor to form a scan line circuit. The resistor is connected between the first pixel of the scan line and the voltage input terminal of the scan line, so that the gate voltage entering the TFT in the first pixel deforms. The voltage of the TFT decreases when it is turned off, minimizing screen flickering and inhomogeneous brightness due to the capacitor charge coupling effect between the first pixel and the last pixel on a scan line.
1. A scan line circuit that solves screen flicker, imperfect exposure junctions and inhomogeneous brightness in a TFT-LCD, which includes a plurality of perpendicular scan lines and a plurality of horizontal data lines, each of the scan lines connecting a plurality of pixel TFTs in a row and each of the data lines connecting a plurality of pixel TFTs in a column to form an array of the pixel TFTs, and a drain of the each pixel TFTs connecting a liquid crystal capacitor and a storage capacitor, wherein each of the scan line comprises:
gate voltage deformation means for deforming a gate input voltage waveform input from an input terminal of the scan line, the gate voltage deformation means located only between the gate of the first pixel TFT in the row and the input terminal of the scan line.
2. The circuit of claim 1 , wherein the gate voltage deformation means comprises a resistor.
3. The circuit of claim 2 , wherein the resistance of the resistor is in the range between 10 Ω/sq and 100 Ω)/sq.
4. The circuit of claim 1 , wherein the gate voltage deformation means comprises an ITO thin film.
5. The circuit of claim 1 , wherein the gate voltage deformation means comprises a TFT that the TFT's gate connects the TFT's source directly.
6. A scan line circuit that solves screen flicker, imperfect exposure junctions and inhomogeneous brightness in a TFT-LCD, which includes a plurality of perpendicular scan lines and a plurality of horizontal data lines, each of the scan lines connecting a plurality of pixel TFTs in a row and each of the data lines connecting a plurality of pixel TFTs in a column to form an array of the pixel TFTs, and a drain of the each pixel TFTs connecting a liquid crystal capacitor and a storage capacitor, wherein each of the scan line comprises:
gate voltage deformation means for, generating a deformed gate voltage waveform transmitted to the pixel TFTs connected to the same scan line, the gate voltage deformation means located between the gate of the first pixel TFT in the row and the input terminal of the scan line.
7. The circuit of claim 6 , wherein the gate voltage deformation means comprises a resistor.
8. The circuit of claim 7 , wherein the resistance of the resistor is in the range between 10 Ω/sq and 100 Ω/sq.
9. The circuit of claim 6 , wherein the gate voltage deformation means comprises an ITO thin film.
10. The circuit of claim 6 , wherein the gate voltage deformation means comprises a TFT that the TFT's gate connects the TFT's source directly.