Tuner of the type having zero intermediate frequency and corresponding control process
View Patent ↗A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/amplifier stage being fixed.
1. A process for controlling a tuner having a zero intermediate frequency and comprising an analog circuit, a digital circuit, and an analog/digital conversion stage connected therebetween, the analog circuit comprising a frequency transposition stage and a first controlled-gain amplifier stage connected upstream thereof, the process comprising:
calculating an overall power of an entire signal having a plurality of channels received by the tuner during a phase of initialization;
comparing the calculated overall power in the digital circuit with a first reference value corresponding to a desired power at a location in the analog circuit;
adjusting a gain of the first controlled-gain amplifier stage based upon a deviation between the calculated overall power and the first reference value; and
selecting one of the plurality of channels during a phase of normal operation after the gain of the first controlled-gain amplifier stage has been adjusted.
2. A process according to claim 1 , wherein calculating the overall, power comprises calculating an overall mean power.
3. A process according to claim 1 , wherein the desired power at the location in the analog receiver is a maximum power.
4. A process according to claim 1 , wherein the gain of the first controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated overall power and the first reference value.
5. A process according to claim 1 , wherein the analog circuit further comprises a baseband filter connected to an output of the frequency transposition stage, and a second controlled-gain amplifier stage connected to an output of the baseband filter; and the process further comprising:
calculating a channel power of the selected channel during the phase of normal operation;
comparing the calculated channel power with a second reference value corresponding to a desired channel power desired at an input of the analog/digital conversion stage; and
adjusting a gain of the second controlled-gain amplifier stage based upon a deviation between the calculated channel power and the second reference value.
6. A process according to claim 5 , wherein calculating the channel power comprises calculating a mean channel power.
7. A process according to claim 5 , wherein the desired channel power at the input of the analog/digital conversion stage is a maximum channel power.
8. A process according to claim 5 , wherein the gain of the second controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated channel power and the second reference value.
9. A process according to claim 5 , wherein calculating the overall power of the entire signal is based upon a signal available between an output of the first controlled-gain amplifier stage and an input of the frequency transposition stage.
10. A process according to claim 5 , wherein calculating the overall power of the entire signal is performed in the digital circuit.
11. A process according to claim 5 , wherein the first controlled-gain amplifier stage comprises an attenuator for attenuating the entire signal.
12. A process for controlling a tuner having a zero intermediate frequency and comprising an analog circuit, a digital circuit, and an analog/digital conversion stage connected therebetween, the analog circuit comprising a first controlled-gain amplifier stage and a second controlled-gain amplifier stage with a frequency transposition stage connected therebetween, the process comprising:
calculating an overall power of an entire signal having a plurality of channels received by the tuner during a phase of initialization;
adjusting a gain of the first controlled-gain amplifier stage based upon a deviation between the calculated overall power and a first reference value corresponding to a desired power at a location in the analog circuit;
selecting one of the plurality of channels during a phase of normal operation after the gain of the first controlled-gain amplifier stage has been adjusted;
calculating a channel power of the selected channel during the phase of normal operation; and
adjusting a gain of the second controlled-gain amplifier stage based upon a deviation between the calculated channel power and a second reference value corresponding to a desired channel power at an input of the analog/digital conversion stage.
13. A process according to claim 12 , wherein calculating the overall power comprises calculating an overall mean power.
14. A process according to claim 12 , wherein the desired power at the location in the analog receiver is a maximum power.
15. A process according to claim 12 , wherein the gain of the first controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated overall power and the first reference value.
16. A process according to claim 12 , wherein adjusting the gain of the first controlled-gain amplifier stage comprises comparing the calculated overall power with the first reference value.
17. A process according to claim 12 , wherein calculating the channel power comprises calculating a mean channel power.
18. A process according to claim 12 , wherein the desired channel power at the input of the analog/digital conversion stage is a maximum channel power.
19. A process according to claim 12 , wherein the gain of the second controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated channel power and the second reference value.
20. A process according to claim 12 , wherein adjusting the gain of the second controlled-gain amplifier stage comprises comparing the calculated channel power with the second reference value.
21. A process according to claim 12 , wherein calculating the overall power of the entire signal is based upon a signal available between an output of the first controlled-gain amplifier stage and an input of the frequency transposition stage.
22. A process according to claim 12 , wherein calculating the overall power of the entire signal is performed iii the digital circuit.
23. A tuner having a zero intermediate frequency and comprising:
an analog circuit comprising
a first controlled-gain amplifier stage having an input for receiving an entire signal having a plurality of channels,
a signal routing circuit having an input for receiving the entire signal from said first controlled-gain amplifier stage, and
a frequency transposition stage connected to a first output of said signal routing circuit;
an analog/digital conversion stage having an input being connected to an output of said frequency transposition stage or to a second output of said signal routing circuit;
a digital circuit connected to said analog/digital conversion stage and comprising a first adjustment circuit for adjusting a gain of said first controlled-gain amplifier stage based upon comparing a calculated overall power of the entire signal with a first reference value corresponding to a desired power at a location in said analog circuit; and
a control circuit connected to said signal routing circuit for connecting the input to the second output thereof for adjusting a deviation between the calculated overall power and the first reference value during a phase of initialization, and for connecting the input to the first output thereof for selecting one of the plurality of channels during a phase of normal operation after the gain of said first controlled-gain amplifier stage has been adjusted.
24. A tuner according to claim 23 , wherein the calculated overall power comprises an overall mean power.
25. A tuner according to claim 23 , wherein the desired power at the location in the analog receiver is a maximum power.
26. A tuner according to claim 23 , wherein the gain of said first controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated overall power and the first reference value.
27. A tuner according to claim 23 , wherein said digital circuit further comprises:
a first calculator circuit for providing the calculated overall power; and
a first comparison circuit for comparing the calculated overall power with the first reference value.
28. A tuner according to claim 23 , further comprising a baseband filter connected to an output of said frequency transposition stage.
29. A tuner according to claim 23 , wherein said analog circuit further comprises a second controlled-gain amplifier stage connected to an output of said frequency transposition stage.
30. A tuner according to claim 29 , wherein said digital circuit further comprises a second adjustment circuit for adjusting a gain of said second controlled-gain amplifier stage based upon a deviation between a calculated channel power of a selected channel and a second reference value.
31. A tuner according to claim 30 , wherein the calculated channel power comprises a mean channel power.
32. A tuner according to claim 30 , wherein the gain of said second controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated channel power and the second reference value.
33. A tuner according to claim 30 , wherein said digital circuit further comprises:
a second calculation circuit for providing the calculated channel power during a phase of normal operation; and
a second comparison circuit for comparing the calculated channel power with the second reference value corresponding to a desired channel power at an input of said analog/digital conversion stage.
34. A tuner according to claim 33 , wherein the desired channel power is a maximum channel power.
35. A tuner according to claim 23 , further comprising a semiconductor substrate such that said analog circuit, said analog/digital conversion stage, and said digital circuit are integrated on said semiconductor substrate.
36. A satellite digital television receiver comprising:
a tuner having a zero intermediate frequency and comprising
an analog circuit comprising
a first controlled-gain amplifier stage having an input for receiving an entire signal having a plurality of channels,
a signal routing circuit having an input for receiving the entire signal from said first controlled-gain amplifier stage, and
a frequency transposition stage connected to a first output of said signal routing circuit;
an analog/digital conversion stage having an input being connected to an output of said frequency transposition stage or to a second output of said signal routing circuit;
a digital circuit connected to said analog/digital conversion stage and comprising a first adjustment circuit for adjusting a gain of said first controlled-gain amplifier stage based upon comparing a calculated overall power of the entire signal with a first reference value corresponding to a desired power at a location in said analog circuit; and
a control circuit connected to said signal routing circuit for connecting the input to the second output thereof for adjusting a deviation between the calculated overall power and the first reference value during a phase of initialization, and for connecting the input to the first output thereof for selecting one of the plurality of channels during a phase of normal operation after the gain of said first controlled-gain amplifier stage has been adjusted.
37. A satellite digital television receiver according to claim 36 , wherein the calculated overall power comprises an overall mean power.
38. A satellite digital television receiver according to claim 36 , wherein the desired power at the location in the analog receiver is a maximum power.
39. A satellite digital television receiver according to claim 36 , wherein the gain of said first controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated overall power and the first reference value.
40. A satellite digital television receiver according to claim 36 , wherein said digital circuit further comprises:
a first calculator circuit for providing the calculated overall power; and
a first comparison circuit for comparing the calculated overall power with the first reference value.
41. A satellite digital television receiver according to claim 36 , further comprising a baseband filter connected to an output of said frequency transposition stage.
42. A satellite digital television receiver according to claim 36 , wherein said analog circuit further comprises a second controlled-gain amplifier stage connected to an output of said frequency transposition stage.
43. A satellite digital television receiver according to claim 42 , wherein said digital circuit further comprises a second adjustment circuit for adjusting a gain of said second controlled-gain amplifier stage based upon a deviation between a calculated channel power of a selected channel and a second reference value.
44. A satellite digital television receiver according to claim 43 , wherein the calculated channel power comprises a mean channel power.
45. A satellite digital television receiver according to claim 43 , wherein the gain of said second controlled-gain amplifier stage is adjusted to minimize the deviation between the calculated channel power and the second reference value.
46. A satellite digital television receiver according to claim 43 , wherein said digital circuit further comprises:
a second calculation circuit for providing the calculated channel power during a phase of normal operation; and
a second comparison circuit for comparing the calculated channel power with the second reference value corresponding to a desired channel power at an input of said analog/digital conversion stage.
47. A satellite digital television receiver according to claim 46 , wherein the desired channel power is a maximum channel power.