Granted Patent
Utility
US 6,404,370
· Confirmation No. 6661
SEMICONDUCTOR INTEGRATED CIRCUIT REALIZING ELECTRICAL INTERFACE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-04-10 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-04-10 | SPEC |
Specification | 22 | View | |
| 2001-04-10 | CLM |
Claims | 4 | View | |
| 2001-04-10 | ABST |
Abstract | 1 | View | |
| 2001-04-10 | DRW |
Drawings-only black and white line drawings | 7 | View | |
| 2001-04-10 | OATH |
Oath or Declaration filed | 5 | View |
Inventors
Yutaka Terada
Osaka, JAPAN
Hironori Akamatsu
Osaka, JAPAN
Satoshi Takahashi
Osaka, JAPAN
Takashi Hirata
Osaka, JAPAN
Yoshihide Komatsu
Osaka, JAPAN
Attorneys & Agents of Record
Classification
USPC
341/143
H04L12/40052
H04L12/40032
Prosecution
- Examiner
- YOUNG, BRIAN K
- Art Unit
- 2819
- Docket No.
- 60188-059
- Confirmation No.
- 6661
Foreign Priority
2000-111753
·
2000-04-13
·
JAPAN
Publication
- Pub. No.
- US20010032328A1
- Pub. Date
- 2001-10-18
Patent Term Adjustment
0days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2020-05-27
CHANGE OF NAME
Recorded 2020-03-18
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-04-10
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Quick Facts
- Patent No.
- US 6,404,370
- App. No.
- 09/828,936
- Filed
- 2001-04-10
- Granted
- 2002-06-11
- Pub. No.
- US20010032328A1
- Examiner
- YOUNG, BRIAN K
- Art Unit
- 2819
- PTA
- 0 days
External Links