Integrated access device controller
View Patent ↗A network processor ( 12 ) for a voice over Internet protocol phone integrates a universal serial bus port ( 56 ), a pair of IEEE 802.3 MACs ( 70 a ), a repeater ( 70 b ), and a pair of pulse code modulation (PCM) ports ( 24 ) such that the network processor can be combined with other peripherals to transmit both voice and data over an Internet protocol network ( 13 ).
1. A processor for use in a Voice over Internet Protocol (VoIP) telephone, comprising:
a bus;
a processor core coupled to the bus;
a packet handler coupled to the bus, the packet handler including plurality of first ports for interfacing to one or more workstations;
a voice handler coupled to the bus, the voice handler including at least one second port for interfacing to a telephone;
a cell/frame handler coupled to the bus, the cell frame handler adapted to couple to one or more packet networks; and
a peripheral control processor coupled to the bus for handling interrupts and direct memory access (DMA) requests;
wherein the peripheral control processor is a programmable, interrupt-driven microcontroller for data transfer and peripheral control, and includes instructions for DMA and bit handling.
2. A processor according to claim 1 , wherein the packet handler includes a bus bridge for interfacing to the bus, a 10/100bT interface, a wireless local area network (LAN) interface, a Universal serial bus interface, and a home phoneline networking alliance interface.
3. A processor according to claim 2 , wherein the voice handler includes a bus bridge for interfacing to the bus, one or more pulse code modulation (PCM) ports, a mailbox, and a digital signal processor (DSP) core.
4. A processor according to claim 3 , wherein the cell/frame handler includes:
a frame handler for sending and receiving frames over the one or more packet networks;
an asynchronous transfer mode (ATM) cell handler for sending and receiving data over ATM networks; and
an encryption unit for encrypting the data.
5. A method for providing a Voice over Internet Protocol (VoIP) processor comprising:
providing a bus;
providing a processor core coupled to the bus;
providing a packet handler coupled to the bus, the packet handler including plurality of ports for interfacing to one or more workstations;
providing a voice handler coupled to the bus, the voice handler including at least one port for interfacing to a telephone;
providing a cell/frame handler coupled to the bus, the cell frame handler adapted to couple to one or more packet networks; and
providing a peripheral control processor coupled to the bus for handling interrupts and DMA requests;
wherein the peripheral control processor is a programmable, interrupt-driven microcontroller for data transfer and peripheral control, and includes instructions for DMA and bit handling.
6. A method according to claim 5 , wherein providing the packet handler including providing a bus bridge for interfacing to the bus, a 10/100bT interface, a wireless LAN interface, a Universal serial bus interface, and a home phoneline networking alliance interface.
7. A method according to claim 6 , wherein providing the voice handler including providing a bus interface for interfacing to the bus, one or more PCM ports, a mailbox, and a DSP core.
8. A method according to claim 7 , wherein providing the cell/frame handler including:
providing a frame handler for sending and receiving frames over one or more packet networks;
an ATM cell handler for sending and receiving data over ATM networks; and
an encryption unit for encrypting the data.
9. A telecommunications system, comprising:
a local area network;
a workstation;
a telephone; and
a Voice over Internet Protocol interface coupling the telephone and the workstation to the local area network, the VoIP interface including a VoIP processor, the VoIP processor including
a bus,
a processor core coupled to the bus,
packet handler coupled to the bus, the packet handler including plurality of ports for interfacing to the workstation,
voice handler coupled to the bus, the voice handler including at least one port for interfacing to the telephone,
cell/frame handler coupled to the bus, the cell frame handler adapted to couple to the local area network, and
peripheral control processor coupled to the bus for handling interrupts and DMA requests;
wherein the peripheral control processor is a programmable, interrupt-driven microcontroller for data transfer and peripheral control, and includes instructions for DMA and bit handling.
10. A telecommunications system according to claim 9 , wherein the packet handler includes a bus bridge for interfacing to the bus, a 10/100bT interface, a wireless LAN interface, a Universal serial bus interface, and a home phoneline networking alliance interface.
11. A telecommunications system according to claim 10 , wherein the voice handler includes a bus interface for interfacing to the bus, one or more PCM ports, a mailbox, and a DSP core.
12. A telecommunications system according to claim 11 , wherein the cell/frame handler includes:
a frame handler for sending and receiving frames over the one or more packet networks;
an ATM cell handler for sending and receiving data over ATM networks; and
an encryption unit for encrypting the data.
13. A method of providing a telecommunications system, comprising:
providing a local area network;
providing a workstation;
providing a telephone; and
providing a Voice over Internet Protocol interface coupling the telephone and the workstation to the local area network, the VoIP interface including a VoIP processor, the VoIP processor including
a bus,
a processor core coupled to the bus,
a packet handler coupled to the bus, the packet handler including plurality of ports for interfacing to the workstation,
voice handler coupled to the bus, the voice handler including at least one port for interfacing to the telephone,
a cell/frame handler coupled to the network, the cell frame handler adapted to couple to the local area network, and
a peripheral control processor coupled to the bus for handling interrupts and DMA requests;
wherein the peripheral control processor is a programmable, interrupt-driven microcontroller for data transfer and peripheral control, and includes instructions for DMA and bit handling.
14. A telecommunications method according to claim 13 , wherein providing the packet handler including providing a bus bridge for interfacing to the bus, a 10/100bT interface, a wireless LAN interface, a Universal serial bus interface, and a home phoneline networking alliance interface.
15. A telecommunications method according to claim 14 , wherein providing the voice handler includes providing a bus interface for interfacing to the bus, one or more PCM ports, a mailbox, and a DSP core.
16. A telecommunications method according to claim 15 , wherein providing the cell/frame handler includes:
providing a frame handler for sending and receiving frames over one or more packet networks;
an ATM cell handler for sending and receiving data over ATM networks; and
an encryption unit for encrypting the data.
17. A processor according to claim 1 , wherein the bus is a flexible peripheral interconnect bus.
18. A processor according to claim 1 , wherein the processor core is a microcontroller having two pipelines that support integer and load/store operations, and a third pipeline that supports optimized digital signal processor loop operation.