Granted Patent
Utility
US 6,385,127
· Confirmation No. 1986
SYNCHRONOUS SEMICONDUCTOR DEVICE AND METHOD FOR LATCHING INPUT SIGNALS
Inventor:
Shinichiro Ikeda
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-04-12 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-04-12 | SPEC |
Specification | 22 | View | |
| 2001-04-12 | CLM |
Claims | 4 | View | |
| 2001-04-12 | ABST |
Abstract | 1 | View | |
| 2001-04-12 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2001-04-12 | OATH |
Oath or Declaration filed | 5 | View |
Inventors
Shinichiro Ikeda
Kasugai-shi, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/233
Prosecution
- Examiner
- MAI, SON LUU
- Art Unit
- 2818
- Customer No.
- 23850
- Docket No.
- 010367
- Confirmation No.
- 1986
Foreign Priority
2000-352636
·
2000-11-20
·
JAPAN
Publication
- Pub. No.
- US20020060945A1
- Pub. Date
- 2002-05-23
Patent Term Adjustment
0days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-04-27
CHANGE OF NAME
Recorded 2010-08-02
from
FUJITSU LIMITED
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2008-12-05
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Quick Facts
- Patent No.
- US 6,385,127
- App. No.
- 09/832,851
- Filed
- 2001-04-12
- Granted
- 2002-05-07
- Pub. No.
- US20020060945A1
- Examiner
- MAI, SON LUU
- Art Unit
- 2818
- PTA
- 0 days
External Links