Granted Patent B1

US 6,940,516 · App. 09/837,043 · Granted Sep 6, 2005

Abstract

Claims (51)

1. A video controller raster engine that receives video data from a frame buffer and renders formatted data to a display in a computer system, the raster engine comprising:

a first in first out (FIFO) memory that interfaces a host bus in the computer system with the raster engine and obtains video data from the frame buffer via the host bus to provide video data to a video pipeline;

a first input counter that has a first input counter value indicative of video data obtained from the frame buffer;

a first output counter that has a first output counter value indicative of video data provided to the video pipeline; and

a control logic system, associated with the FIFO memory, that provides an underflow indication according to the first input and output counter values;

wherein the underflow signal indicates an existing underflow condition when the first input and output counter values are equal for at least two cycles of a host clock.

2. The raster engine of claim 1 , wherein the underflow indication comprises an underflow signal indicating at least one of an existing underflow condition, an anticipated underflow condition, and a raster engine lockup condition.

3. The raster engine of claim 2 , wherein the control logic system provides the underflow signal to a host processor in the computer system.

4. The raster engine of claim 2 , wherein the underflow signal indicates one of an existing underflow condition and an anticipated underflow condition when the first input and output counter values are within a threshold value of each other.

5. The raster engine of claim 4 , wherein the raster engine comprises an underflow threshold value register programmable by a host processor in the computer system, and wherein the control logic system obtains the threshold value from the threshold value register, and compares the threshold value with the difference between the first input and output counter values.

6. The raster engine of claim 4 , wherein the underflow signal indicates an existing underflow condition when the first input and output counter values are equal, and an anticipated underflow condition when the first input and output counter values are within a threshold value of each other.

7. The raster engine of claim 6 , wherein the FIFO memory obtains video data from the frame buffer according to the host clock and provides video data to the video pipeline according to a video clock, and wherein the underflow signal indicates an anticipated underflow condition when the first input and output counter values are within a threshold value of each other for at least two cycles of the host clock.

8. The raster engine of claim 1 , wherein the control logic system comprises a first logic circuit adapted to subtract the first output counter value from the first input counter value to obtain a difference value, and wherein the control logic system provides an underflow indication if the comparison is less than or equal to a threshold value.

9. The raster engine of claim 8 , wherein the control logic system comprises a second logic circuit adapted to compare the difference value with the threshold value.

10. The raster engine of claim 8 , wherein the FIFO memory obtains video data from the frame buffer according to a host clock and provides video data to the video pipeline according to a video clock, and wherein the control logic system provides an underflow indication if the comparison is less than or equal to a threshold value for at least two cycles of the host clock.

11. The raster engine of claim 1 , wherein the FIFO memory obtains video data from the frame buffer according to a host clock and provides video data to the video pipeline according to a video clock and wherein the control logic system provides the underflow indication when the first input and output counter values are equal for at least two cycles of the host clock, and when the first input and output counter values are within a threshold value of each other for at least two cycles of the host clock.

12. The raster engine of claim 1 , further comprising:

a second input counter having a second input counter value indicative of video data obtained from the frame buffer; and

a second output counter having a second output counter value indicative of video data provided to the video pipeline;

wherein the raster engine selectively performs dual scan operation with the FIFO memory to provide interleaved first and second video data to the video pipeline represented by the first and second output counter values; and

wherein the control logic system provides an underflow indication according to the first input and output counter values and second input and output counter values.

13. The raster engine of claim 12 , wherein the underflow indication comprises an underflow signal indicating at least one of an existing underflow condition, an anticipated underflow condition, and a raster engine lockup condition.

14. The raster engine of claim 13 , wherein the underflow signal indicates one of an existing underflow condition and an anticipated underflow condition when the first input and output counter values are within a threshold value of each other or when the second input and output counter values are within the threshold value of each other.

15. The raster engine of claim 12 , wherein the raster engine comprises an underflow threshold value register programmable by a host processor in the computer system, and wherein the control logic system obtains a threshold value from the threshold value register, and compares the threshold value with the difference between the first input and output counter values and with the difference between the second input and output counter values.

16. The raster engine of claim 12 , wherein the FIFO memory obtains video data from de frame buffer according to a host clock and provides video data to the video pipeline according to a video clock, and wherein the control logic system provides the underflow indication when the first input and output counter values are equal for at least two cycles of the host clock, when the first input and output counter values are within a threshold value of each other for at least two cycles of the host clock, when the second input and output counter values are equal for at least two cycles of the host clock, and when the second input and output counter values are within a threshold value of each other for at least two cycles of the host clock.

17. A video underflow detection system that indicates an underflow condition in a video controller raster engine with a first in first out (FIFO) memory that interfaces a host bus and adapted to obtain video data from a frame buffer via the host bus and to provide video data to a video pipeline, the underflow detection system comprising:

a control logic system associated with the FIFO memory, a first input counter having a first input counter value indicative of video data obtained from the frame buffer, and a first output counter having a first output counter value indicative of video data provided to the video pipeline;

wherein the control logic system provides an underflow indication according to the first input and output counter values, the underflow signal indicates an existing underflow condition when the first input and output counter values are equal for at least two cycles of a host clock.

18. The underflow detection system of claim 17 , wherein the underflow indication comprises an underflow signal indicating at least one of an existing underflow condition, an anticipated underflow condition, and a raster engine lockup condition.

19. The underflow detection system of claim 18 , wherein the underflow signal indicates one of an existing underflow condition and an anticipated underflow condition when the first input and output counter values are within a threshold value of each other.

20. The underflow detection system of claim 19 , wherein the underflow signal indicates an existing underflow condition when the first input and output counter values are equal, and an anticipated underflow condition when the first input and output counter values are within a threshold value of each other.

21. The underflow detection system of claim 20 , wherein the FIFO memory obtains video data from the frame buffer according to the host clock and provides video data to the video pipeline according to a video clock, and wherein the underflow signal indicates an anticipated underflow condition when the first input and output counter values are within a threshold value of each other for at least two cycles of the host clock.

22. The underflow detection system of claim 17 , wherein the control logic system comprises a first logic circuit that subtracts the first output counter value from the first input counter value to obtain a difference value, and wherein the control logic system provides an underflow indication if the comparison is less than or equal to a threshold value.

23. The underflow detection system of claim 22 , wherein the control logic system comprises a second logic circuit that compares the difference value with the threshold value.

24. The underflow detection system of claim 22 , wherein the FIFO memory obtains video data from the frame buffer according to a host clock and provides video data to the video pipeline according to a video clock, and wherein the control logic system provides an underflow indication if the comparison is less than or equal to a threshold value for at least two cycles of the host clock.

25. A method of detecting underflow conditions ill a video controller raster engine, comprising:

obtaining an input counter value indicative of video data obtained from a frame buffer;

obtaining an output counter value indicative of video data provided from a memory to a video pipeline in the raster engine;

performing a comparison of the input and output counter values; and

selectively providing an underflow indication according to the input and output counter value comparison, selectively providing an underflow indication comprises providing an underflow signal if the difference value is less than or equal to the threshold for at least two cycles of the host clock.

26. The method of claim 25 , wherein selectively providing an underflow indication comprises providing an underflow signal if the input and output counter values are within a threshold value of each other.

27. The method of claim 25 , wherein performing a comparison of the input and output counter values comprises:

subtracting the output counter value from the input counter value to obtain a difference value; and

comparing the difference value with a threshold value.

28. The method of claim 27 , wherein selectively providing an underflow indication comprises providing an underflow signal if the difference value is less than or equal to the threshold.

29. The method of claim 28 , wherein the raster engine obtains video data from the frame buffer according to the host clock.

30. A system for detecting underflow conditions in a video controller raster engine, comprising:

means for obtaining an input counter value indicative of video data obtained from a frame buffer;

means for obtaining an output counter value indicative of video data provided from a memory to a video pipeline in the raster engine;

means for performing a comparison of the input and output counter values; and

means for selectively providing an underflow indication according to the input and output counter value comparison, the underflow signal indicates at least one of an existing underflow condition when the first input and output counter values are equal for at least two cycles of the host clock, and an anticipated underflow condition when the first input and output counter values are within a threshold value of each other for at least two cycles of a host clock.

Assignments (7)