Granted Patent
Utility
US 6,459,319
· Confirmation No. 9957
VARIABLE DELAY CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME
Inventor:
Atsumasa Sako
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-04-30 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-04-30 | SPEC |
Specification | 14 | View | |
| 2001-04-30 | CLM |
Claims | 2 | View | |
| 2001-04-30 | ABST |
Abstract | 1 | View | |
| 2001-04-30 | DRW |
Drawings-only black and white line drawings | 7 | View | |
| 2001-04-30 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Atsumasa Sako
Kawasaki, JAPAN
Attorneys & Agents of Record
Classification
USPC
327/276
Foreign Priority
2000-156843
·
2000-05-26
·
JAPAN
Publication
- Pub. No.
- US20010045855A1
- Pub. Date
- 2001-11-29
Patent Term Adjustment
-49days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-04-27
CHANGE OF NAME
Recorded 2010-07-22
from
FUJITSU LIMITED
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2008-12-12
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