Echo and crosstalk cancellation
View Patent ↗A cancellation system comprises a channel circuit ( 11 ) for each noise source, such as echo in a particular cable pair. There are only eighty taps per channel, in two blocks (n_echo_a, f_echo_a). Each block is preceded by a variable delay line comprising blocks of registers cascaded so that a delay value of 0 to 40 clock cycles can be chosen. The delay value is determined by determining an optimum position for each tap block. This is achieved by determining a maximum coefficient sum for a number of windows. Taps from other channels are used during training, so that there is a total of 160 taps for each channel during training to enable the optimum positions to be determined.
1. A cancellation system for echo or crosstalk noise in a communications transceiver for a plurality of channels, the system comprising:
a channel circuit including taps for each channel and means for training the taps by setting coefficient values, the taps being arranged in at least one block having a fixed number of taps;
at least some of the channel circuits each having insufficient taps for a full span;
each of said channel circuits further including a variable delay line connected in series with the taps; and
the training means including means for determining an optimum position for each tap block to set the length of each variable delay line.
2. The cancellation system as claimed in claim 1 , wherein the training means is configured to share taps from another channel circuit when training each channel circuit in order to achieve a full span for each channel during training.
3. The cancellation system as claimed in claim 1 , wherein each channel circuit includes a plurality of variable delay lines separated by taps.
4. The cancellation system as claimed in claim 1 , wherein the training means is configured to determine a coefficient sum for each of a plurality of candidate windows, and choosing the window providing the maximum coefficient sum.
5. The cancellation system as claimed in claim 1 , wherein the training means is configured to determine an optimum position for each block subject to pre-set constraints.
6. The cancellation system as claimed in claim 5 , wherein a constraint is a maximum length for the variable delay line.
7. The cancellation system as claimed in claim 5 , wherein a constraint is that tap blocks do not overlap.
8. The cancellation system as claimed in claim 1 , wherein each channel circuit includes, in series, a near variable delay line, a near tap block, a far variable delay line, and a far tap block.
9. The cancellation system as claimed in claim 1 , wherein each variable delay line has cascaded register blocks linked by multiplexers including means for bypassing a register block or feeding data through said register block according to training control signals setting a delay length.
10. The cancellation system as claimed in claim 1 , wherein the training means includes an adaptation module for at least one tap block.
11. The cancellation system as claimed in claim 10 , wherein at least some adaptation modules include means for training two or more tap blocks.
12. A cancellation system for echo or crosstalk noise in a communication transceiver for a plurality of channels, the system comprising:
a channel circuit including taps for each channel and means for training the taps by setting coefficient values;
at least some of the channel circuits each having insufficient taps for a full span;
each of said channel circuits further including a variable delay line connected in series with the taps; and
the training means including means for sharing taps from another channel circuit when training each channel circuit in order to achieve a full span for each channel during training.
13. The cancellation system as claimed in claim 12 , wherein the training means further includes means for determining an optimum position for each tap to set the length of the variable delay line.
14. The cancellation system as claimed in claim 13 , wherein the means for determining includes means for determining a coefficient sum for each of a plurality of candidate windows, and choosing the window providing the maximum coefficient sum.
15. The cancellation system as claimed in claim 13 , wherein the training means includes means for determining an optimum position for each block subject to pre-set constraints.
16. The cancellation system as claimed in claim 15 , wherein a constraint is a maximum length for the variable delay line.
17. The cancellation system as claimed in claim 15 , wherein a constraint is that tap blocks do not overlap.
18. A cancellation system for echo or crosstalk noise in a communications transceiver for a plurality of channels, the system comprising:
a channel circuit having taps for each channel and a tap coefficient training circuit for training the taps by setting coefficient values, each channel circuit including, in series, a near variable delay line, a near tap block, a far variable delay line, and a far tap block;
at least some of the channel circuits each having insufficient taps for a full span; and
the tap coefficient training circuit being configured to set a length of each variable delay line so that positions of the taps are optimised.
19. A cancellation system for echo or crosstalk noise in a communications transceiver for a plurality of channels, the system comprising:
a channel circuit having taps for each channel and a tap coefficient training circuit for training the taps by setting coefficient values, each channel circuit including, in series, a near variable delay line, a near tap block, a far variable delay line, and a far tap block;
at least some of the channel circuits each having insufficient taps for a full span;
each of said channel circuits further including a variable delay line connected in series with the taps;
the tap coefficient training circuit being configured to set a length of each variable delay line so that positions of the taps are optimised; and
each variable delay line having cascaded register blocks linked by multiplexers including means for bypassing a register block or feeding data through said register block according to training signals setting a delay length.