Scheduling the dispatch of cells in multistage switches
View Patent ↗A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided.
1. A combination for use in a multi-stage switch, the combination comprising:
a) a plurality of central modules, each including outgoing links towards output modules including a plurality of output ports;
b) a plurality of input modules, each including
i) virtual output queues, and
ii) outgoing links coupled with each of the plurality of central modules; and
c) means for matching a non-empty virtual output queue of the input module with an outgoing link in the input module; and
d) means for matching the outgoing link of the input module with an outgoing link of one of the central modules,
wherein high switch throughput can be achieved without speedup of the central modules.
2. The combination of claim 1 wherein the means for matching a non-empty virtual output queue of an input module with an outgoing link in the input module include:
i) means for broadcasting a request for the non-empty virtual output queue to an arbiter for each of the outgoing links of the input module;
ii) for each of the outgoing links of the input module, an arbiter for selecting a non-empty virtual output queue that broadcast a request;
iii) means for sending a grant to an arbiter for the selected non-empty virtual output queue; and
iv) for the selected non-empty virtual output queue, an arbiter for selecting an outgoing link from among the one or more outgoing links that sent a grant.
3. The combination of claim 2 wherein the means for matching a non-empty virtual output queue of an input module with an outgoing link in the input module performs the match within one cell time slot.
4. The combination of claim 2 wherein the arbiter of each of the outgoing links of the input module for selecting a non-empty virtual output queue that broadcast a request, includes a pointer updated in accordance with a round robin discipline.
5. The combination of claim 4 wherein the pointer moves through groups of virtual output queues, before moving through virtual output queues within each group.
6. The combination of claim 1 wherein the means for matching a non-empty virtual output queue of the input module with an outgoing link in the input module performs multiple matching iterations within one cell time slot.
7. The combination of claim 1 wherein the means for matching the outgoing link with an outgoing link of one of the central modules include:
i) means for broadcasting a request for the outgoing link of the input module to an arbiter for each of the outgoing links of the central modules that lead towards an output port associated with the virtual output queue matched with the outgoing link of the input module;
ii) for each of the outgoing links of the central module, an arbiter for selecting an outgoing link of the input module that broadcast a request; and
iii) means for sending a grant to the selected outgoing link of the input module.
8. The combination of claim 7 wherein the arbiter of each of the outgoing links of the central module for selecting an outgoing link that broadcast a request, includes a pointer updated based on a round robin discipline.
9. The combination of claim 1 wherein there are:
k input modules, each having n input ports, n×k virtual output queues, and m outgoing links.
10. The combination of claim 9 wherein, n×k virtual output queues of each input module are grouped into k groups of n virtual output queues.
11. An input module for use a multi-stage switch including a plurality of central modules, the input module comprising:
a) virtual output queues;
b) outgoing links coupled with each of the plurality of central modules; and
c) means for matching a non-empty virtual output queue of an input module with an outgoing link in the input module, the means for matching including
i) means for broadcasting a request for the non-empty virtual output queue to an arbiter for each of the outgoing links of the input module,
ii) for each of the outgoing links of the input module, an arbiter for selecting a non-empty virtual output queue that broadcast a request,
iii) means for sending a grant to an arbiter for the selected non-empty virtual output queue, and
iv) for the selected non-empty virtual output queue, an arbiter for selecting an outgoing link from among the one or more outgoing links that sent a grant.
12. The input module of claim 11 wherein the means for matching a non-empty virtual output queue of an input module with an outgoing link in the input module performs such matching within one cell time slot.
13. The input module of claim 11 wherein the arbiter of each of the outgoing links of the input module for selecting a non-empty virtual output queue that broadcast a request, is pointer updated in accordance with a round robin discipline.
14. The input module of claim 13 wherein the pointer moves through groups of virtual output queues, before moving through virtual output queues within each group.
15. The input module of claim 11 wherein means for matching a non-empty virtual output queue of an input module with an outgoing link in the input module repeats such matching within one cell time slot.
16. The input module of claim 11 wherein there are k input modules, each having n input ports, n×k virtual output queues, and m outgoing links.
17. The input module of claim 16 wherein the n×k virtual output queues of each input module are grouped into k groups of n virtual output queues.