Multi-service segmentation and reassembly device that maintains only one reassembly context per active output port
View Patent ↗A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
1. A method, comprising:
receiving on an integrated circuit from a switch fabric a first number of groups of switch cells, each switch cell having a switch header and a data payload, each of the groups being destined for one of a second number of output ports of the integrated circuit, the first number being greater than the second number;
storing each of the data payloads of the first number of groups into a corresponding one of a plurality of buffers;
retrieving from the plurality of buffers the data payloads of one of the groups of switch cells destined for each of the output ports, and outputting from the integrated circuit the data payloads retrieved such that a reassembled packet is transmitted onto a fiber optic cable for each of the groups of switch cells retrieved, the reassembled packet of a group comprising the data payloads of the switch cells of the group, the data payloads of no more than one group for each output port being output at any one time; and
maintaining a reassembly context for each group of data payloads being retrieved from the plurality of buffers, each group of data payloads being retrieved being destined for a different one of the output ports such that the integrated circuit maintains no more than one reassembly context per output port, a reassembly context including a partial byte count and a partial CRC.
2. The method of claim 1 , wherein the output ports are logical output ports associated with a single physical output port.
3. The method of claim 1 , wherein the data payloads of one of the groups of switch cells are AAL5 adaptation layer cells, one of the AAL5 adaptation layer cells including a trailer, the trailer including a CRC, the integrated circuit not checking the CRC in the trailer prior to storing the data payloads of the group into the plurality of buffers.
4. The method of claim 1 , wherein the integrated circuit includes a reassembly block, and wherein each reassembly context includes a running byte count value, the running byte count value of the reassembly context for an output port being updated as each successive data payload of the switch cells of a group destined for the output port passes into the reassembly block, the reassembly block using the running byte count value to remove padding from a last of the data payloads, the last of the data payloads being marked by an EOP bit.
5. An integrated circuit having one or more active output ports, comprising:
a memory manager that stores chunks of information into buffers in a payload memory, all the buffers being of equal size, some of the chunks including cell information, others of the chunks including packet information;
a reassembly engine that receives said chunks from the memory manager and that performs only one reassembly process at any given time for each active output port, the reassembly engine maintaining substantially no more than one reassembly context for each active output port, a reassembly context including a partial byte count and a partial CRC; and
a mode control register, wherein placing first configuration information in the mode control register causes the integrated circuit to operate in an ingress mode, and wherein placing second configuration information in the mode control register causes the integrated circuit to operate in an egress mode.
6. The integrated circuit of claim 5 , wherein the reassembly engine comprises:
a port calendar;
a data memory comprising a plurality of buffers;
an enqueue state machine for queuing said chunks into said data memory on a per output port basis; and
a dequeue state machine for dequeuing said chunks from said data memory in accordance with an output port identifier received from the port calendar.
7. An integrated circuit having one or more active output ports, comprising:
a memory manager that stores chunks of information into buffers in a payload memory, all the buffers being of equal size, some of the chunks including cell information, others of the chunks including packet information;
reassembly means for receiving said chunks from the memory manager and for performing one reassembly process per active output port such that substantially no more than one reassembly context is maintained for each active output port a reassembly context including a partial byte count and a partial CRC; and
a mode control register that stores configuration information, wherein the integrated circuit is configured in an ingress mode if first configuration information is stored in the mode control register, and wherein the integrated circuit is configured in an egress mode if second configuration information is stored in the mode control register.
8. The integrated circuit of claim 7 , wherein the reassembly means processes a chunk in one of a plurality of ways as determined by type information, the type information for a chunk being passed from the memory manager to the reassembly means along with the chunk.