Semiconductor device with a bipolar transistor, and method of manufacturing such a device
View Patent ↗A semiconductor device includes a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. Here, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor is provided with a pn clamping diode which is formed between the partial region and the collector region.
1. A method of manufacturing a semiconductor device which comprises a first semiconductor region of a first conductivity type with a first connection conductor forming a collector region of a bipolar transistor, a second semiconductor region of a second conductivity type opposed to the first conductivity type with a second connection conductor forming a base region of the transistor, and a third semiconductor region of the first conductivity type with a third connection conductor forming an emitter region of the transistor; said method comprising:
forming the first semiconductor region of the first conductivity type;
forming the second semiconductor region on the first semiconductor region, the second semiconductor region having a partial region with a smaller flux of dopant atoms than another part of the second semiconductor region;
forming the third semiconductor region which lies recessed in the other part, and outside the partial region, of the second semiconductor region; and
providing first, second and third connection conductors to the first, second and third regions wit a connection conductor respectively, wherein the second conductor is exclusively connected to the second semiconductor region and adjoins the partial region of he second semiconductor region.
2. A method as claimed in claim 1 , characterized in that the partial region of the second semiconductor region is formed below the second connection conductor and is given a smaller thickness and a lower doping concentration than those in the other region.
3. A method as claimed in claim 1 , characterized in that the partial region of the second semiconductor region is given a smaller thickness than that in the other region.
4. A method as claimed in claim 1 , characterized in that the partial region of the second semiconductor region is formed by means of ion implantation.
5. The method of claim 1 , wherein the second semiconductor region is above the first semiconductor region and wherein the first connection conductor adjoins a bottom side of the first region opposing the second semiconductor region.
6. The method of claim 1 , wherein forming the second semiconductor region includes forming the partial region of the second semiconductor region having a doping concentration at least five to ten times lower than the doping concentration of the other part of the second semiconductor region.
7. The method of claim 1 , wherein forming the second semiconductor region includes forming the partial region of the second semiconductor region having a thickness at least as thin as half the thickness of the other part of the second semiconductor region.
8. The method of claim 1 , further including forming a fourth semiconductor region of the second conductivity type in the partial region of the second semiconductor region wherein the fourth semiconductor region makes contact with the second connection conductor.