Apparatus and method for interfacing with a high speed bi-directional network using a shared memory to store packet data
View Patent ↗A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.
1. A method of processing data in a bi-directional processing device, the method comprising:
(a) receiving said data by a first processor from a bi-directional interface, said first processor operative to perform a first task on said data thereby resulting in processed data;
(b) storing said processed data in a shared memory by said first processor, said shared memory comprising first and second banks, wherein one of said first and second banks is accessible to said first processor and the other of said first and second banks is accessible to a second processor;
(c) mirroring said processed data stored by said first processor in said one of said first and second banks to the other of said first and second banks;
(d) retrieving said processed data from said other of said first and second banks of said shared memory by said second processor operative to perform a second task on said processed data thereby resulting in secondarily processed data; and
(e) transmitting, selectively, said secondarily processed data to said bi-directional interface from said second processor.
2. The method of claim 1 , wherein said first task comprises at least one of inspection and analysis.
3. The method of claim 1 , wherein said second task comprises taking an action on said processed data.
4. The method claim 3 , wherein said taking an action comprises at least one of deleting, modifying and transmitting said processed data.
5. The method of claim 1 , wherein each of said first and second processors is characterized by a bi-directional bandwidth, said method further comprising utilizing substantially all of said bi-directional bandwidth for uni-directional data flow.
6. The method of claim 1 , wherein said storing further comprises storing said processed data such that said second processor is unaware of how said processed data was stored in said shared memory.
7. The method of claim 1 , wherein said first and second processors comprise network processors.
8. The method of claim 1 , wherein said transmitting is further based on a result of said second task.
9. A bi-directional data processor comprising:
a first processor coupled with a bi-directional interface and operative to receive data from said bi-directional interface and perform a first task on said data thereby resulting in processed data;
a shared memory coupled with said first processor, said shared memory comprising first and second banks, wherein one of said first and second banks is accessible to said first processor, wherein said first processor is further operative to store said processed data in said one of said of said first and second banks of said shared memory;
mirroring logic coupled with said first processor and said first and second banks and operative to mirror said processed data stored by said first processor in said one of said first and second banks to the other of said first and second banks; and
a second processor coupled with said shared memory and said bi-directional interface, said second processor operative to retrieve said stored processed data from said other of said first and second banks of said shared memory, perform a second task on said stored processed data thereby resulting in secondarily processed data and selectively transmit said secondarily processed data back to said bi-directional interface.
10. The bi-directional data processor of claim 9 , wherein said first task comprises at least one of inspection and analysis.
11. The bi-directional data processor of claim 9 , wherein said second task comprises taking an action on said stored processed data.
12. The bi-directional data processor claim 11 , wherein said taking an action comprises at least one of deleting, modifying and transmitting said data.
13. The bi-directional data processor of claim 9 , wherein each of said first and second processors are characterized by a bi-directional bandwidth, substantially all of said bi-directional bandwidth being utilized for uni-directional data flow.
14. The bi-directional data processor of claim 9 , wherein said second processor is unaware of how said processed data was stored in said shared memory.
15. The bi-directional data processor of claim 9 , wherein said first and second processors comprise network processors.
16. The bi-directional data processor of claim 9 , wherein the selective transmission by said second processor is further based on a result of said second task.
17. An apparatus for processing a bi-directional dataflow comprising:
first processor means for receiving data from a bi-directional interface and performing a first task on said data thereby resulting in processed data;
shared memory means coupled with said first processor, said shared memory comprising first and second banks, wherein one of said first and second banks is accessible by said first processor means, wherein said first processor is further operative to store said processed data in said one of said first and second banks of said shared memory means;
memory mirroring means coupled with said first processor and said first and second banks and operative to mirror said processed data stored by said first processor in said one of said first and second banks to the other of said first and second banks; and
second processor means coupled with said shared memory means and operative to retrieve said stored processed data from said other of said first and second banks of said shared memory means, perform a second task on said processed data, thereby resulting in secondarily processed data, and selectively transmit said secondarily processed data to said bi-directional interface.