Device and method for generating and executing compressed programs of a very long instruction word processor

1. A method for controlling functional units in a processor, the method comprising:

a configuration step, in which a sequence of primary instruction words consisting of multiple instruction word parts and originating from a translation of a program code is compressed and stored as a sequence of related program words; and

a subsequent execution step,

wherein sequential secondary instruction words consisting of a plurality of instruction word parts and having the full instruction word width needed to control all functional units are generated from the sequence of related program words,

wherein the configuration step is configured so that a program word ( 7 ) has a first characteristic ( 10 ) of a primary instruction word ( 5 ) from a first reference group ( 11 ) of preceding primary instruction words ( 5 ), which has the greatest similarity to the primary instruction word ( 5 ) associated with the program word ( 7 ), and contains instruction word parts ( 6 ) that differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the first characteristic ( 10 ), and

wherein in the subsequent execution step comprises:

storing a second group ( 12 ) of secondary instruction words ( 9 ) corresponding in number to the first reference group ( 11 ).

wherein each secondary instruction word is provided with a second characteristic ( 13 ),

wherein using the first characteristic ( 10 ) contained in the program word ( 7 ), a particular secondary instruction word ( 9 ) from the second group ( 12 ) is associated with the primary instruction word ( 5 ) via the associated second; characteristic ( 13 ), and

generating a specific secondary instruction word ( 9 ) corresponding to the program word ( 7 ) so that the instruction word parts ( 6 ) contained in the program word ( 7 ) are exchanged in the particular secondary instruction word ( 9 ) from the second group ( 12 ); and

the second group of secondary instruction words,

wherein the configuration step consists of forming and storing previously generated complete Very Long Instruction Words as the first reference group of preceding primary instruction words and the subsequent execution step comprises dynamic updating of the stored second group of secondary instruction words, and wherein the generated specific secondary instruction ( 9 ) is executed by the functional units.

2. The method in accordance with claim 1 , wherein:

the first reference group ( 11 ) consists of a first number of primary instruction words ( 5 ) that directly precede the primary instruction word ( 5 ) associated with the program word ( 7 ); and

the second group ( 12 ) consists of a second number of secondary instruction words ( 9 ) that is at least equal to the first number, where, prior to the generation of the next sequential secondary instruction word ( 9 ), each most recent secondary instruction word ( 9 ), is appended to the second group ( 12 ) as the last word, and the first secondary instruction word ( 9 ) to have been added and that is in excess of the second number is removed from the second group ( 12 ).

3. The method in accordance with claim 1 , further comprising replacing the particular secondary instruction word ( 9 ) in the second group ( 12 ) with the newly generated specific secondary instruction word ( 9 ) in that the latter is stored in place of the secondary instruction word that was used for its generation.

4. The method in accordance with claim 2 , further comprising excluding the newly generated specific secondary instruction word ( 9 ) from the store of the second group of secondary instruction words ( 12 ).

5. The method in accordance with claim 1 , wherein the first characteristic ( 10 ) is formed as a minimum code distance between the primary instruction word belonging to the current program word and the primary instruction word with the greatest similarity.

6. The method in accordance with 1 , wherein the second characteristic ( 13 ) comprises an address corresponding to the first characteristic that is the address of a preceding secondary instruction word in a memory ( 14 ) that is used for storage of the second group ( 12 ).

7. The method in accordance with claim 1 , wherein a plurality of program words ( 7 ) are used to assemble secondary instruction words ( 9 ) that require more than the number of instruction words ( 9 ) stored in one program word ( 7 ) for the secondary instruction word ( 9 ) used for generation.

8. The method in accordance with claim 7 , wherein the instruction word parts ( 6 ) are compressed in one program word ( 7 ) by reducing the bit width to the extent that it is possible to represent the instruction word parts ( 6 ), and wherein multiple program words are used when instruction word parts ( 6 ) occur that require a greater bit width in order to be represented.

9. The method in accordance with claim 8 , wherein the width of the instruction word parts ( 6 ) in the program word ( 7 ) is reduced by half, and up to two program words are provided for representation of the instruction word parts ( 6 ).