Patent Application
Utility
App. No. 09/876,051
· Confirmation No. 9015
Logic determination device for semiconductor integrated device and logic determination method
Inventor:
Masaru Sanada
Abandoned -- Failure to Respond to an Office Action
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-06-08 | TRNA |
Transmittal of New Application | 4 | View | |
| 2001-06-08 | SPEC |
Specification | 23 | View | |
| 2001-06-08 | CLM |
Claims | 9 | View | |
| 2001-06-08 | ABST |
Abstract | 1 | View | |
| 2001-06-08 | DRW |
Drawings-only black and white line drawings | 11 | View | |
| 2001-06-08 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Masaru Sanada
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
372/8
Prosecution
- Examiner
- LANDAU, MATTHEW C
- Art Unit
- 2815
- Customer No.
- 30743
- Docket No.
- MA-488-US
- Confirmation No.
- 9015
Foreign Priority
175969/2000
·
2000-06-12
·
JAPAN
Publication
- Pub. No.
- US20010050936A1
- Pub. Date
- 2001-12-13
No related applications found.
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-02-12
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Quick Facts
- App. No.
- 09/876,051
- Filed
- 2001-06-08
- Pub. No.
- US20010050936A1
- Examiner
- LANDAU, MATTHEW C
- Art Unit
- 2815
External Links