Wireless computer network including a mobile appliance containing a single chip transceiver

1. A wireless computer data network, comprising:

a plurality of mobile, wireless appliances;

at least one base station connected to the Internet; and

an interface circuit for establishing an ad-hoc radio communication link amongst the plurality of mobile, wireless appliances and the base station;

wherein, the interface circuit operates with carrier frequencies in the 5 GHz band and data is transferred with orthogonal frequency division multiplexing (OFDM), and wherein each of the plurality of mobile, wireless appliances comprises:

a single integrated circuit that implements a complete radio transceiver for wireless connection with the interface circuit, wherein said single integrated circuit comprises:

at least two independent frequency synthesizers connected in a double-conversion superheterodyne configuration.

2. A wireless computer data network, comprising:

a plurality of mobile, wireless appliances;

at least one base station connected to the Internet; and

an interface circuit for establishing an ad-hoc radio communication link amongst the plurality of mobile, wireless appliances and the base station;

wherein, the interface circuit operates with carrier frequencies in the 5 GHz band and data is transferred with orthogonal frequency division multiplexing (OFDM), and wherein each of the plurality of mobile, wireless appliances comprises:

a single integrated circuit that implements a complete ratio transceiver for wireless connection with the interface circuit, wherein said single integrated circuit comprises:

a pair of on-chip synthesizers that each have a voltage-controlled oscillator and phase-locked loop that can be operated independently for each conversion stage, or operated in offset mode; and

an input for bypassing the on-chip synthesizers and to inject external reference frequencies during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling.

3. A wireless computer data network that includes a plurality of untethered mobile units that provide for ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard;

wherein, each mobile unit and base station includes a radio transceiver fully integrated on a single semiconductor chip with a double-conversion superheterodyne type receiver portion and a two-stage up-conversion transmitter that shares the same intermediate and local oscillator frequencies;

wherein, a pair of on-chip synthesizers are included that each have a voltage-controlled oscillator and phase-locked loop that can be operated independently for each conversion stage, or operated in offset mode; and

wherein, an input is provided for injecting external reference frequencies during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling.

4. A single-chip radio transceiver for operation in the 5 GHz radio spectrum, comprising:

a double-conversion superheterodyne radio receiver;

a two-stage up-conversion radio transmitter;

a first frequency synthesizer connected to supply a higher local oscillator reference frequency to both the receiver and transmitter;

a second frequency synthesizer independent of the first frequency synthesizer, and connected to supply a lower local oscillator reference frequency to both the receiver and transmitter;

a plurality of ramp and bias generators for selectively and gradually applying operating power to various parts of the receiver, transmitter, and the first and second frequency synthesizers; and

a microcomputer connected to monitor and control each of the plurality of ramp and bias generators, receiver, transmitter, and the first and second frequency synthesizers.

5. The single-chip radio transceiver of claim 4 , wherein:

the microcomputer compensates for manufacturing production variations by adjustments output to the plurality of ramp and bias generators.

6. The single-chip radio transceiver of claim 4 , wherein:

the microcomputer compensates for temperature variations according to device characteristic models.

7. The single-chip radio transceiver of claim 4 , further comprising:

an input port provided for injecting an external reference frequency during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling;

wherein, the microcomputer thereafter compensates during device operation for production and temperature variations.

8. A wireless computer data network, comprising:

a wireless appliance means for mobile roaming within reach of an ad-hoc wireless communication link;

at least one base station means for connecting the wireless appliance means through to the Internet over said ad-hoc wireless communication link; and

an interface means for establishing said ad-hoc radio communication link, and for operating with carrier frequencies in the 5 GHz band, and for transferring orthogonal frequency division multiplexing (OFDM) data,

wherein each of the wireless appliance means comprises:

a single integrated circuit means for implementing a single radio transceiver portion of the interface means, wherein said single integrated circuit means comprises:

at least two independent frequency synthesizers means for connection in a double-conversion superheterodyne configuration.

9. A wireless computer data network, comprising:

a wireless appliance means for mobile roaming within reach of an ad-hoc wireless communication link;

at least one base station means for connecting the wireless appliance means through to the Internet over said ad-hoc wireless communication link; and

an interface means for establishing said ad-hoc radio communication link, and for operating with carrier frequencies in the 5 GHz band, and for transferring orthogonal frequency division multiplexing (OFDM) data,

wherein each of the wireless appliance means comprises:

a single integrated circuit means for implementing a single radio transceiver portion of the interface means, wherein said single integrated circuit means comprises:

a pair of on-chip synthesizer means for voltage-controlled oscillator and phase-locked loop functions that can be operated independently for each conversion stage, or operated in offset mode; and

an input means for bypassing the on-chip synthesizers and to inject external reference frequencies during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling.

10. A method of operating a wireless computer data network that includes a plurality of untethered mobile units that provide for ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard, the method comprising the steps of;

completely integrating a radio transceiver in each mobile unit and base station on a single semiconductor chip with a double-conversion superheterodyne type receiver portion and a two-stage up-conversion transmitter that shares the same intermediate and local oscillator frequencies;

including a pair of on-chip synthesizers on said chip that each have a voltage-controlled oscillator and phase-locked loop that can be operated independently for each conversion stage, or operated in offset mode; and

providing an input for injecting external reference frequencies during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling.

11. A single-chip radio transceiver for operation in the 5 GHz radio spectrum, comprising:

means for a double-conversion superheterodyne radio reception;

means for a two-stage up-conversion radio transmission;

means for synthesizing and connecting a first frequency synthesizer to supply a higher local oscillator reference frequency to both the reception and transmission means;

means for connecting a second frequency synthesizer independent of the first frequency synthesizer, and for connecting to supply a lower local oscillator reference frequency to both the receiver and transmitter of the transceiver;

ramp and bias generator means for selectively and gradually applying operating power to various parts of the receiver, transmitter, and the first and second frequency synthesizers; and

microcomputer means for monitoring and controlling ramp and bias generator means, the reception and transmission means, and said first and second frequency synthesizers.

12. The single-chip radio transceiver of claim 11 , wherein:

the microcomputer means includes means for compensating any manufacturing production variations by adjusting an output provided to the ramp and bias-generator means.

13. The single-chip radio transceiver of claim 11 , wherein:

the microcomputer means compensates for temperature variations according to device characteristic models.

14. The single-chip radio transceiver of claim 11 , further comprising:

an input means for injecting an external reference frequency during voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling;

wherein, the microcomputer means thereafter compensates during device operation for production and temperatue variations.