Variable length instruction pipeline
View Patent ↗A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.
1. An variable length instruction pipeline comprising:
a first pipeline stage;
a first expansion stage coupled to the first pipeline stage;
a second pipeline stage coupled to the first pipeline stage and the first expansion stage, wherein the second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage; and
a second expansion stage coupled to the first pipeline stage and the first expansion stage and wherein the first expansion stage is configured to selectively receive instructions from the first pipeline stage or the second expansion stage.
2. The variable length instruction pipeline of claim 1 , further comprising a multiplexer coupled between the first expansion stage and the second pipeline stage and between the first pipeline stage and the second pipeline stage.
3. The variable length instruction pipeline of claim 1 , further comprising a multiplexer coupled between the second expansion stage and the first expansion stage and between the first pipeline stage and the first expansion stage.
4. The variable length instruction pipeline of claim 1 , further comprising a third pipeline stage coupled to the second pipeline stage.
5. The variable length instruction pipeline of claim 1 , wherein the first pipeline stage is part of an instruction fetch and decode unit.
6. The variable length instruction pipeline of claim 5 , wherein the instruction fetch and issue unit further comprises an instruction fetch stage coupled to the first pipeline stage.
7. The variable length instruction pipeline of claim 1 , wherein the second pipeline stage is a decode stage.
8. The variable length instruction pipeline of claim 1 configured to process integer instructions.