IP Library Granted Patent US 6,952,746
Granted Patent B2
US 6,952,746 · App. 09/881,922 · Granted Oct 4, 2005

Method and system for system performance optimization via heuristically optimized buses

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Quick Facts
Patent No.
US 6,952,746
App. No.
09/881,922
Granted
Oct 4, 2005
Kind
B2
Abstract

A method and system for enhancing performance of a bus in a data processing system is described. The method includes monitoring priority of processes in an operating system queue along with data flow through adapters coupled to the bus in a data processing system, determining if increased bus performance is desirable, and adjusting bus parameters to enhance the performance of the bus if increased bus performance is desirable.

Claims (29)

1. A method for enhancing performance of a bus in a data processing system, comprising:

monitoring data flow through an adapter coupled to the bus in a data processing system;

determining if increased bus performance is desirable; determining whether performance of the bus is a function of an external device connected to the adapter; and

handing off control to a code module which enhances performance of the bus if increased bus performance is desirable.

2. The method of claim 1 , further comprising: determining the performance by examining prior throughput of data of the adapter.

3. The method of claim 1 , further comprising:

changing, in small incremental steps, hardware settings upstream to the adapter; and

after an optimum performance point is achieved, maintaining current state.

4. The method of claim 1 , further comprising:

reaching a decision based upon prior performance parameters of other devices coupled to the bus.

5. The method of claim 1 , further comprising:

determining a priority of a set of adapters, including the adapter, coupled to the bus.

6. The method of claim 5 , further comprising:

changing the priority throughput of at least one of the set of adapters.

7. The method of claim 1 , further comprising:

simultaneously monitoring throughput of the adapter.

8. A system for optimizing the performance of a bus, comprising:

a first bus coupled to at least one central processing limit (CPU) having a code module embedded therein;

at least one input/output (I/O) adapter coupled to the first bus;

a driver for the at least one input/output (I/O) adapter residing in the at least one central processing unit (CPU); and

a bus monitor coupled to a hardware bus control unit residing in the code module wherein information acquired by the bus monitor is processed, a determination is made as to whether the performance of the bus is a function of an external device connected to the input/output adapter, and a decision is made to increase adapter throughput.

9. The system of claim 8 , further comprising a second bus disposed to be monitored by the bus monitor, and connected to the at least one input/output (I/O) adapter.

10. The system of claim 8 , wherein the code module comprises:

a performance optimizer unit, wherein a process management queue is scanned, a determination as to weather the process management queue have a high priority I/O process;

a process management limit coupled to the performance optimizer unit; and

a hardware bus control unit, wherein bus performance is being read, coupled to the performance optimizer unit.

11. The system of claim 10 , further comprising device driver, wherein at least one bus parameter in the I/O adapter is changed, coupled to the process management unit.

12. The system of claim 10 , wherein the hardware bus control unit changes at least one bus parameter.

13. The system of claim 8 , wherein the hardware bus control unit is coupled to an I/O bus hub.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2010
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TREND MICRO INCORPORATED
Reel/Frame 024411/0551 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2001
From: CAPPS, LOUIS BENNIE JR.; DANIELS, SCOTT LEONARD; MEALEY, BRUCE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 011913/0675 →