Conditionally nonblocking switch of the compressor type
View Patent ↗Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.
1. A method for implementing a class of N×N compressors each serving a connection request to route m incoming signals, m≦N and for enabling the service of any connection request in a nonblocking way on the condition that the connection request is compliant to certain constraints, where each compressor in the class has a set of connection states and has an array of N input ports with N distinct input addresses and an array of N output ports with N distinct output addresses wherein the m incoming signals arrive at m distinct ones of the input ports determining m active input addresses and are destined for corresponding m distinct ones of the output ports determining m active output addresses, the method for each of the compressors comprising:
configuring an N×N k-stage interconnection network comprises (i) k stages of nodes, (ii) an interstage exchange between any succeeding two of the k stages, (iii) an input exchange, and (iv) an output exchange, and each node is filled with a switch of N−1 or fewer input ports and output ports, and
routing the incoming signals from the m distinct input ports to the corresponding m distinct output ports by activating one of the connection states such that the activated one of the connection states accommodates the connection request subject to said certain constraints on the connection request, wherein said certain constraints on the connection request are that: (1) the m active output addresses are consecutive upon a rotation of the ordering of the N output addresses, and (2) the correspondence between the m active input addresses and the m active output addresses is order preserving after the rotation,
said class excluding (i) those having a switch constructed from the reverse banyan network of switching cells appended with the inverse shuffle exchange and (ii) those having a switch constructed from the reverse shuffle-exchange network of switching cells appended with the inverse shuffle exchange.
2. The method as recited in claim 1 wherein each switch is a compressor.
3. The method as recited in claim 1 wherein k=2 such that: (1) said N×N k-stage switching network becomes a two-stage interconnection network composed of a first stage of nodes being the input nodes and a second stage of nodes being the output nodes, an interstage exchange, and an output exchange, corresponding to the interstage exchange, appended to the network, and (2) each switch is a compressor.
4. The method as recited in claim 3 wherein the two-stage interconnection network is configured as a 2X interconnection network.
5. The method as recited in claim 1 wherein said N×N k-stage switching network is configured as a recursive 2X interconnection network having nodes and wherein each switch is a compressor.
6. The method as recited in claim 5 wherein each of the nodes is a cell and each cell is filled with a 2×2 compressor.
7. The method as recited in claim 6 wherein said 2×2 compressor is a switching cell.
8. The method as recited in claim 1 wherein said N×N k-stage switching network is configured as a recursive 2X interconnection network of cells with each cell filled with a 2×2 compressor.
9. The method as recited in claim 8 wherein the 2×2 compressor is a switching cell.
10. The method as recited in claim 1 wherein said N×N k-stage switching network is configured as a banyan-type network whose trace and guide are both monotonically decreasing and wherein each of the 2×2 nodes of the banyan-type network is filled with a 2×2 compressor.
11. The method as recited in claims from 10 wherein the 2×2 compressor is a switching cell.
12. The method as recited in claim 1 wherein said N×N k-stage switching network is configured as a recursive plain 2-stage interconnection network of cells appended with a swap exchange and wherein each cell of the network is filled with a 2×2 compressor.
13. The method as recited in claim 12 wherein the 2×2 compressor is a switching cell.
14. The method as recited in claim 1 wherein said N×N k-stage switching network is configured as a divide-and-conquer network of cells appended with a swap exchange and wherein each cell of the network is filled with a 2×2 compressor.
15. A class of N×N compressors each serving a connection request to route m incoming signals, m≦N, and for enabling the service of any connection request in a nonblocking way on the condition that the connection request is compliant to certain constraints, each of the compressors comprising:
an array of N input ports with N distinct input addresses and an array of N output ports with N distinct output addresses wherein the m incoming signals arrive at m distinct ones of the input ports determining m active input addresses and are destined for corresponding m distinct ones of the output ports determining m active output addresses,
an N×N k-stage switching network defined by a set of connection states comprising (i) k stages of nodes, (ii) an interstage exchange between any succeeding two of the k stages, (iii) an input exchange and (iv) an output exchange, and wherein each node is filled with a switch having N−1 or fewer input ports and output ports, and
control circuitry, coupled to the switching network, for routing the incoming signals from the m distinct input ports to the corresponding m distinct output ports by activating one of the connection states such that the activated one of the connection states accommodates the connection request subject to said constraints on the connection request, wherein said constraints on the connection request are that: (1) the m active output addresses are consecutive upon a rotation of the ordering of the N output addresses, and (2) the correspondence between the m active input addresses and the m active output addresses is order preserving after the rotation,
said class excluding (i) those having a switch constructed from the reverse banyan network of switching cells appended with the inverse shuffle exchange and (ii) those having a switch constructed from the reverse shuffle-exchange network of switching cells appended with the inverse shuffle exchange.
16. The compressor as recited in claim 15 wherein each switch is a compressor.
17. The compressor as recited in claim 15 wherein k=2 such that: (1) said N×N k-stage switching network becomes a two-stage interconnection network comprising a first stage of nodes being the input nodes and a second stage of nodes being the output nodes, an interstage exchange, and an output exchange, corresponding to the interstage exchange, appended to the network, and (2) each switch is a compressor.