Data management architecture
A performance optimized RAID Level 3 storage access controller with a unique XOR engine placement at the host/network side of the cache. The invention utilizes multiple data communications channels and a centralized cache memory in conjunction with this unique XOR placement to maximize performance and fault tolerance between a host network and data storage. Positioning the XOR engine at the host/network side of the cache allows the storage devices to be fully independent. Since the XOR engine is placed in the data path and the parity is generated in real-time during cache write transfers, the bandwidth overhead is reduced to zero. For high performance RAID controller applications, a system architecture with minimal bandwidth overhead provides superior performance.
1. A data management architecture comprising:
a) an XOR engine;
b) a host network interface coupled to said XOR engine and for coupling to a host computer system;
c) a cache coupled to said XOR engine;
d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices,
wherein said XOR engine includes:
a first transceiver coupled to said host network interface;
logic means for i) generating an XOR parity byte using said data and appending said parity byte to said data, ii) checking XOR parity, and iii) correcting detected parity errors;
a second transceiver coupled to said cache.
2. The data management architecture defined by claim 1 wherein said host network interface comprises:
a) a physical interface;
b) a protocol engine coupled to the physical interface;
c) a receive buffer coupled to the protocol engine;
d) a transmit buffer coupled to the protocol engine;
e) interface buffers coupled to the transmit and receive buffers;
f) a bus coupled to the protocol engine;
g) a microcontroller coupled to the bus;
h) a memory coupled to the bus.
3. The data management architecture defined by claim 1 wherein said cache comprises:
a plurality of cache segments, each of said cache segments including i) a dual port memory array, ii) a bus expander coupled between said XOR engine and said dual port memory array, iii) a bus funnel coupled between said XOR engine and said dual port memory array, and iv) a buffer coupled between said storage device interface and said dual port memory.
4. The data management architecture defined by claim 1 wherein said storage device interface comprises:
a) a physical interface;
b) a protocol engine coupled to the physical interface;
c) a receive buffer coupled to the protocol engine;
d) a transmit buffer coupled to the protocol engine;
e) interface buffers coupled to the transmit and receive buffers;
f) a bus coupled to the protocol engine;
g) a microcontroller coupled to the bus;
h) a memory coupled to the bus.
5. A data management architecture comprising:
a) an XOR engine;
b) a host network interface coupled to said XOR engine and for coupling to a host computer system;
c) a cache coupled to said XOR engine, said cache including a plurality of cache segments, each of said cache segments including i) a dual port memory array, ii) a bus expander coupled between said XOR engine and said dual port memory array, iii) a bus funnel coupled between said XOR engine and said dual port memory array, and iv) a buffer coupled between said storage device interface and said dual port memory;
d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices,
wherein said XOR engine includes:
a first transceiver coupled to said host network interface;
logic means for i) generating in real time an XOR parity byte using said data and appending said parity byte to said data, ii) checking in real time XOR parity, and iii) correcting in real time detected parity errors;
a second transceiver coupled to said cache.
6. A data management architecture comprising:
a) an XOR engine which operates to generate in real time an XOR parity byte using said data and append said parity byte to said data, ii) check in real time XOR parity, and iii) correct in real time detected parity errors;
b) a host network interface coupled to said XOR engine and for coupling to a host computer system;
c) a cache coupled to said XOR engine;
d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices.
7. The data management architecture defined by claim 6 wherein said host network interface comprises:
a) a physical interface;
b) a protocol engine coupled to the physical interface;
c) a receive buffer coupled to the protocol engine;
d) a transmit buffer coupled to the protocol engine;
e) interface buffers coupled to the transmit and receive buffers;
f) a bus coupled to the protocol engine;
g) a microcontroller coupled to the bus;
h) a memory coupled to the bus.
8. The data management architecture defined by claim 6 wherein said cache comprises:
a plurality of cache segments, each of said cache segments including i) a dual port memory array, ii) a bus expander coupled between said XOR engine and said dual port memory array, iii) a bus funnel coupled between said XOR engine and said dual port memory array, and iv) a buffer coupled between said storage device interface and said dual port memory.
9. The data management architecture defined by claim 6 wherein said storage device interface comprises:
a) a physical interface;
b) a protocol engine coupled to the physical interface;
c) a receive buffer coupled to the protocol engine;
d) a transmit buffer coupled to the protocol engine;
e) interface buffers coupled to the transmit and receive buffers;
f) a bus coupled to the protocol engine;
g) a microcontroller coupled to the bus;
h) a memory coupled to the bus.
10. A data management architecture comprising:
a) an XOR engine;
b) a host network interface coupled to said XOR engine and for coupling to a host computer system;
c) a cache coupled to said XOR engine;
d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices,
wherein said XOR engine includes:
a first transceiver coupled to said host network interface;
logic means for i) generating in real time an XOR parity byte using said data and appending said parity byte to said data, ii) checking in real time XOR parity, and iii) correcting in real time detected parity errors;
a second transceiver coupled to said cache.
11. A data management architecture comprising:
a) an XOR engine;
b) a host network interface coupled to said XOR engine and for coupling to a host computer system;
c) a cache coupled to said XOR engine, said cache including a plurality of cache segments, each of said cache segments including i) a dual port memory array, ii) a bus expander coupled between said XOR engine and said dual port memory array, iii) a bus funnel coupled between said XOR engine and said dual port memory array, and iv) a buffer coupled between said storage device interface and said dual port memory;
d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices,
wherein said XOR engine includes:
a first transceiver coupled to said host network interface;
logic means for i) generating in real time an XOR parity byte using said data and appending said parity byte to said data, ii) checking in real time XOR parity, and iii) correcting in real time detected parity errors;
a second transceiver coupled to said cache.