Software controlled ring voltage generator

1. A ring voltage generator, comprising:

a first counter connectable to an external clock, to generate a frequency signal;

a microprocessor interface connectable to a microprocessor;

a multiplexer to selectively pass the frequency signal from the first counter or a programming signal from the microprocessor interface;

a random access memory to store a set of values to generate a ring voltage waveform; and

a second counter to receive values from the RAM and to generate an output pulse train representative of the values.

2. The ring voltage generator of claim 1 , and further comprising:

a microprocessor interface for programming the RAM.

3. The ring voltage generator of claim 2 , and further comprising:

a multiplexer for selectively passing signals from the microprocessor interface or the first counter.

4. The ring voltage generator of claim 1 , and further comprising:

a divider between the first counter and the RAM.

5. The ring voltage generator of claim 1 , and further comprising:

a third counter between the first counter and the RAM, the third counter operating at a predetermined fraction of the first counter.

6. The ring voltage generator of claim 1 , and further comprising:

a flip flop to latch the output of the second counter.

7. A ring voltage generator, comprising:

a random access memory (RAM) for storing a series of values indicative of pulse frequency;

a rate counter to generate a count signal at a predetermined ringer frequency from an external clock; and

a pulse width modulator counter connected to receive data values from the RAM, the PWM counter to generate a pulse train to control a ringer.

8. The ring voltage generator of claim 7 , and further comprising:

a flip flop to latch the output of the PWM counter.

9. The ring voltage generator of claim 7 , and further comprising:

a microprocessor interface;

a multiplexer connected between the microprocessor interface and the RAM and between the rate counter and the RAM, to selectively pass a signal from the microprocessor interface or the rate counter to the RAM.

10. A method, comprising:

programming a set of ring voltage values in random access memory (RAM);

reading out values into a counter;

generating a pulse train indicative of the values as a ring voltage waveform,

wherein generating a pulse train comprises:

receiving a RAM value from the RAM;

counting down to zero from the received RAM value; and

generating a pulse when the counting down reaches zero,

latching pulse output in flip flop; and

resetting the flip flop to a low signal catch time a RAM value is received from the RAM.

11. The method of claim 10 , wherein reading out values into a counter comprises:

dividing an external clock to obtain a signal at a frequency of a ringer;

generating a RAM address in a RAM address counter from the signal; and

accessing the ring voltage value at the generated address.

12. The method of claim 10 , and further comprising:

dividing the signal again to obtain a second reduced frequency; and

accessing the ring voltage value at the generated address a plurality of times in succession.

13. The method of claim 10 , and further comprises:

counting down catch received RAM value a predetermined number of times before receiving another RAM value.

14. A method, comprising:

programming a set of ring voltage values in random access memory (RAM);

reading out values into a counter;

generating a pulse train indicative of the values as a ring voltage waveform; and

reprogramming at least a portion of the set of ring voltage values to adjust the ring voltage waveform.

15. A method, comprising:

programming a set of ring voltage a values in randown access memory (RAM);

reading out values into a counter;

generating a pulse train indicative of the values as a ring voltage waveform; and

reprogramming at least a portion of the set of ring voltage values to adjust the ring voltage waveform.

16. The method of claim 15 , wherein reprogramming comprises:

blocking the signal at the frequency of the ringer; and

passing a reprogramming signal through a microprocessor interface to the RAM.

17. A method, comprising:

programming a random access memory (RAM) with a set of values to generate a ring voltage waveform;

generating a ring voltage waveform from the set of values,

dividing a received external clock to obtain a frequency corresponding to a ring voltage waveform frequency;

reading the set of values from the RAM;

supplying each of the set of RAM values to a counter sequentially;

counting down in the counter each received RAM value;

generating a digital high pulse when the counter reaches zero; and

resetting the pulse to zero before receiving a next RAM value.

18. A method, conspiring:

programming a random access memory (RAM) with a set of values usable to generate a ring voltage waveform;

generating a ring voltage waveform from the set of values; and

reading each RAM value a predetermined number of times before reading a next RAM value;

wherein reading each RAM value a predetermined number of times is accomplished with a RAM address counter running at a fraction of the ring voltage waveform frequency.

19. A method, comprising:

dividing a received clock to a standard ringer frequency;

dividing the standard ringer frequency output;

clearing a flip flop that generates an output signal;

generating a signal indicative of a programming mode or an operating mode;

writing a set of ringer voltage values to a random access memory if the signal indicates a programming mode;

sequentially reading a set of ringer voltage values into a counter if the signal indicates an operating mode; and

generating a train of output pulses corresponding to a ring voltage waveform from the counter if the signal indicates an operating mode.

20. The method of claim 19 , wherein sequentially reading a set of ringer voltage values comprises:

generating a RAM address from the divided standard ringer frequency output; and

reading the RAM value at the generated address into the counter.

21. The method of claim 19 , wherein generating a train of output pulses comprises:

loading the counter with a read RAM value;

counting down the loaded RAM value to zero; and

outputting a pulse when the loaded RAM values is counted down to zero.