Scan insertion testing of ASICs

1. A circuit comprising:

a first input port connectable to a first external clock;

a second input port connectable to a tester and adapted to receive control signals to selectively block and unblock the first input port;

a bi-directional port connectable to a second external clock; and

an output port;

wherein when the first input port is blocked, the second clock transmits a second clock signal to the output port and when the first input port is unblocked, the first clock transmits a first clock signal to the output port.

2. The circuit of claim 1 , wherein the first clock is part of an application specific integrated circuit.

3. The circuit of claim 1 , wherein the second clock is part of an application specific integrated circuit.

4. The circuit of claim 1 , wherein the output port is connectable to internal logic of an application specific integrated circuit.

5. The circuit of claim 1 , and further comprising a first buffer having a first input connected to the first clock via the first input port and a second input connected to the tester via the second input port, and having an output connected to the bi-directional port.

6. The circuit of claim 5 , wherein the first buffer is a tri-state output buffer.

7. The circuit of claim 5 , and further comprising a second buffer having an input connected to the bi-directional port and to the output of the first buffer, and having an output connected to the output port.

8. The circuit of claim 7 , wherein the second buffer is an input buffer.

9. A circuit comprising:

a first buffer having an input port connected to a first external clock, another input port connected to a tester, and an output port;

a bi-directional port connected to the output port of the first buffer and to a second external clock; and

a second buffer having an input port connected to the bi-directional port and to the output port of the first buffer and an output port connectable to external circuitry.

10. The circuit of claim 9 , wherein the first clock is part of an application specific integrated circuit.

11. The circuit of claim 9 , wherein the second clock is part of an application specific integrated circuit.

12. The circuit of claim 9 , wherein the external circuitry comprises logic of an application specific integrated circuit.

13. The circuit of claim 9 , wherein the first buffer is a tri-state output buffer.

14. The circuit of claim 9 , wherein the second buffer is an input buffer.

15. A circuit comprising:

a first buffer to receive a first clock signal and a control signal, the control signal to selectively pass or block the first control signal; and

a second buffer to receive and pass the first clock signal when the first clock signal is passed or to receive a second independent clock signal through a bi-directional port when the first clock signal is blocked.

16. The circuit of claim 15 , wherein the second buffer transmits the first and second clock signals to internal logic of an application specific circuit.

17. The circuit of claim 15 , wherein the first clock signal is received from an application specific integrated circuit.

18. The circuit of claim 15 , wherein the second clock signal is received from an application specific integrated circuit.

19. The circuit of claim 15 , wherein the first buffer is a tri-state output buffer.

20. The circuit of claim 15 , wherein the second buffer is an input buffer.

21. A circuit comprising:

a tri-state output buffer having an input port connected to a clock of an application specific integrated circuit, another input port connected to a tester, and an output port;

a second clock connected to the output port of the tri-state output buffer via a bi-directional port; and

an input buffer having an input port connected to the bi-directional port and to the output port of the tri-state output buffer and an output port connected to logic of the application specific integrated circuit.

22. The circuit of claim 21 , wherein the clock of the application specific integrated circuit is independent from the second clock.

23. A test method comprising:

receiving a control signal indicative of an active or an inactive test mode of a circuit;

coupling a first external clock through the circuit through a first buffer when the test mode is inactive; and

coupling a second external clock through the circuit through a bi-directional port and a second buffer when the test mode is active.

24. The test method of claim 23 , wherein coupling the first external clock comprises coupling a functional clock.

25. The test method of claim 23 , wherein coupling the second external clock comprises coupling a divide/test clock.

26. A test method comprising:

receiving a control signal at a circuit;

selectively blocking a first clock signal received at the circuit based on the control signal;

receiving a second clock signal at a bi-directional port of the circuit;

transmitting the second clock signal when the first clock signal is blocked; and

transmitting the first clock signal when the first clock signal is not blocked.

27. The test method of claim 26 , wherein receiving the control signal comprises receiving the control signal at a buffer.

28. The test method of claim 26 , wherein receiving the control signal comprises receiving the control signal at a tri-state output buffer.

29. The test method of claim 27 , wherein blocking the first clock signal comprises blocking the first clock signal at the buffer.

30. The test method of claim 26 , and further comprising receiving the second clock signal at a buffer from the bi-directional port before transmitting the second clock signal.

31. The test method of claim 26 , and further comprising receiving the second clock signal at an input buffer from the bi-directional port before transmitting the second clock signal.

32. The test method of claim 26 , wherein receiving the control signal comprises receiving the control signal from a tester.

33. The test method of claim 26 , wherein transmitting the first clock signal comprises transmitting the first clock signal to external logic devices.

34. The test method of claim 26 , wherein transmitting the second clock signal comprises transmitting the second clock signal to external logic devices.

35. A test method comprising:

receiving a control signal at a first buffer;

blocking a first clock signal received at the first buffer at the first buffer based on the control signal;

receiving a second clock signal at a second buffer from a bi-directional port; and

transmitting the second clock signal from the second buffer to logic devices.

36. The test method of claim 35 , wherein receiving the control signal comprises receiving the control signal from a tester.

37. The test method of claim 35 , and further comprising receiving another control signal at the first buffer that unblocks the first clock signal.

38. The test method of claim 37 , and further comprising transmitting the first clock signal to the logic devices via the first and second buffers.

39. A test method comprising:

coupling a first external clock to a first input port of a first buffer;

coupling a tester to a second input port of the first buffer;

coupling an output port of the first buffer to a bi-directional port and to an input port of a second buffer;

coupling a second external clock to the bi-directional port;

coupling an output port of the second buffer to internal logic devices;

transmitting a control signal from the tester to the first buffer to block a first clock signal transmitted to the first buffer from the first clock; and

transmitting a second clock signal from the second clock to the internal logic devices via the bi-directional port and the second buffer.

40. The test method of claim 39 , and further comprising receiving another control signal at the first buffer that unblocks the first clock signal.

41. The test method of claim 40 , and further comprising transmitting the first clock signal to the internal logic devices via the first and second buffers.