IP Library Granted Patent US 7,418,034
Granted Patent B2
US 7,418,034 · App. 09/884,256 · Granted Aug 26, 2008

Combined trellis decoder and decision feedback equalizer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,418,034
App. No.
09/884,256
Granted
Aug 26, 2008
Kind
B2
Abstract

An adaptive equalizer comprises a trellis decoder; a mapper coupled to the output of the trellis decoder; and a decision feedback equalizer coupled to the output of the mapper. Each of the taps receives as input via the mapper output from a different one of the stages of the trellis decoder.

Claims (26)

1. An adaptive equalizer comprising:

a Viterbi decoder having 16 stages and producing a decoded output;

a mapper coupled to the decoded output of the Viterbi decoder, the mapper producing a mapped output; and

a decision feedback equalizer coupled to the mapped output, the decision feedback equalizer having more than 16 taps;

wherein 16 of the taps each receive as input via the mapper output from a respective one of the 16 stages of the Viterbi decoder.

2. The adaptive equalizer of claim 1 , further comprising an FIR filter.

3. The adaptive equalizer of claim 1 , wherein at least one tap receives as input via the mapper delayed output from the 16th decoding stage.

4. An adaptive equalizer comprising:

a Viterbi decoder having 16 stages and producing a decoded output;

a mapper coupled to the decoded output, the mapper producing a mapped output; and

a decision feedback equalizer coupled to the mapped output, the decision feedback equalizer having fewer than 16 taps;

wherein each of the taps receives as input via the mapper output from a respective one of the 16 stages of the Viterbi decoder.

5. The adaptive equalizer of claim 4 , wherein the taps receive the output from the earliest “x” decoding stages, where “x” is the number of taps.

6. The adaptive equalizer of claim 5 , wherein an error signal is generated from the 16th decoding stage.

7. An adaptive equalizer comprising:

a trellis decoder producing a decoded output and having 16 stages;

a mapper coupled to the decoded output and having a mapped output; and

a decision feedback equalizer coupled to the mapped output, the decision feedback equalizer having fewer than 16 taps;

wherein each of the taps receives as input via the mapper output from a respective one of the 16 stages of the trellis decoder.

8. The adaptive equalizer of claim 7 , wherein the trellis decoder comprises a Viterbi decoder.

9. An adaptive equalizer, comprising:

an FIR filter;

a trellis decoder coupled to the FIR filter and having a decoded output and M number of stages; and

a mapper;

a decision feedback equalizer coupled to the FIR filter and to the trellis encoder via the mapper, where the decision feedback equalizer comprises N number of taps;

wherein the decoded output is mapped and scaled by the mapper and used by the adaptive equalizer to generate an error signal, and M is not equal to N.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028146/0054 →