Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins
A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.
1. A reconfigurable processor integrated circuit, comprising:
a processor core for operating on a set of instructions to carry out predefined processes;
a plurality of input/output pins;
a plurality of functional input/output blocks each having an input and an output and associated with said processing core to allow said processing core to interface with said plurality of input/output pins, each of said functional input/output blocks having an associated and predetermined functionality, said functionality being the output as a function of the input, the function defined by said functionality, and each of said functional input/output blocks having a requirement for a defined number of said plurality of input/output pins wherein the total of said defined number for all of said plurality of functional input/output blocks exceeds the number of said plurality of input/output pins, wherein said processor core is interfaced with one of said input of each of said functional blocks;
a reconfigurable interface for selectively interfacing between the other of said input or output of said functional input/output blocks and a select one or ones of said plurality of input/output pins, such that said processor core, can be interfaced with said select one or ones of said input/output pins, said reconfigurable interface operable to define how each of said plurality of input/output pins interfaces with said select ones of said plurality of functional input/output blocks and the associated functionality in accordance with configuration information; and
a non-volatile memory for storing said configuration information, such that said stored configuration information can be altered.
2. The reconfigurable processor integrated circuit of claim 1 , wherein said plurality of input/output pins are configured in functional groups.
3. The reconfigurable processor intergrated circuit of claim 1 , wherein said each of said functional input/output blocks has a plurality of inputs and outputs and each of said plurality of said input/output pins can be interfaced with any of said plurality of functional input/output blocks by said reconfigurable interface.
4. The reconfigurable processor integrated circuit of claim 1 , wherein said reconfigurable interface is programmable by said user.
5. The reconfigurable processor integrated circuit of claim 1 , wherein said processor core is a digital processor core and further comprising an analog section for interfacing via input/output analog pins with analog signals and for interfacing with said processor core with a digital interface.
6. The reconfigurable processor integrated circuit of claim 5 , wherein said input/output analog pins are not reconfigurable with said reconfigurable interface.
7. The intergrated circuit of claim 1 , wherein each of said functional input/output blocks has a predetermined functionality associated therewith that is modifiable to modify the associated function.
8. The intergrated circuit of claim 7 , wherein said processor core is operable to input to a select one of said functional input/output blocks on the associated input thereof control information to modify the function associated therewith.
9. The intergrated circuit of claim 7 , wherein said processor core is operable during normal operation of the intergrated circuit of modify the function of one or more of said functional input/output blocks.
10. The intergrated circuit of claim 1 , wherein the one of the inputs and outputs of each of said functional input/output blocks interfaced with said processor core has a special function register associated therewith, such that any signals received from said processor core are stored therein and any signals transmitted to said processor core from the associated one of said functional input/output blocks is stored therein.
11. The integrated circuit of claim 10 , and further comprising a special function register bu for interfacing between said processor core and said special function registers, wherein each of said special function registers has an address associated therewith that is within an address space of said processor core.