Method and apparatus for regulating transceiver power consumption for a transceiver in a communications network
View Patent ↗A method and apparatus for regulating transceiver power consumption for a transceiver in a communications network. Data received by the transceiver is monitored to detect the presence or absence of a received data signal. A transceiver state machine is controlled to regulate transceiver power consumption in response to the presence of absence of the data received.
1. A method of regulating transceiver power consumption for a transceiver in a communications network comprising:
monitoring a data receiver to detect a received data signal; and
controlling a transceiver state machine to regulate transceiver power consumption in response to the presence or absence of a received data signal;
wherein the transceiver state machine comprises a full-on state during which a wake up control signal is sent to power on a transmitter and a power control signal is sent to power on the transceiver, a full-off state during which the wake up signal is sent to power off the transmitter and the power control signal is sent to power off the transceiver, and a pending wake-up on state during which the wake up control signal is sent to power on the transmitter and the power control signal is sent to power off the transceiver, and wherein the transceiver state machine is configured to:
transition from the full-on state to the full-off state after failing to detect a received data signal for a period determined by a first timing circuit;
transition from the full-off state to the pending wake-up on state after failing to detect a received data signal for an additional period determined by the first timing circuit; and
transition from the pending wake-up on state to the full-on state after sending out a data link signal, detecting a first received data signal in response to the data link signal within a first period determined by a second timing circuit, and detecting a second received data signal after detecting the first received data signal within a second period determined by the second signal timing circuit.
2. The method of claim 1 , wherein the transceiver state machine is further configured to transition from the pending wake-up on state to the full-off state after sending out the data link signal and failing to detect a first received data signal within the first period determined by the second signal timing circuit.
3. The method of claim 1 , wherein the transceiver state machine is further configured to transition from the pending wake-up on state to the full-off state after sending out the data link signal, detecting the first received data signal in response to the data link signal within the first period determined by the second timing circuit, and failing to detect a second received data signal after detecting the first received data signal within the second period determined by the second signal timing circuit.
4. The method of claim 1 , wherein monitoring a data receiver to detect a received data signal includes comparing a signal received from the communications network with a reference signal and determining a magnitude of the signal received from the communications network exceeds a magnitude of the reference signal.
5. The method of claim 1 , wherein the transceiver state machine is further configured to transition from the full-off state to the full-on state after detecting a first received data signal within a period determined by a first timing circuit, waiting for a stand-by period determined by a third timing circuit, and detecting a second received data signal after the stand-by period but before a period determined by a fourth data timing circuit.
6. The method of claim 1 , wherein the transceiver state machine is further configured to remain in the full-off state after detecting a first received data signal within a period determined by a first timing circuit, waiting for a stand-by period determined by a third timing circuit, and failing to detect a second received data signal after the stand-by period but before a period determined by a fourth data timing circuit.
7. A transceiver power consumption regulator for a transceiver in a communications network comprising:
a data receiver located on the transceiver to detect a received data signal; and
a transceiver state machine coupled between the data receiver and a transmitter to regulate transceiver power consumption of the transceiver in response to the presence or absence of a received data signal;
wherein the transceiver state machine comprises a full-on state during which a wake up control signal is sent to power on the transmitter and a power control signal is sent to power on the transceiver, a full-off state during which the wake up signal is sent to power off the transmitter and the power control signal is sent to power off the transceiver, and a pending wake-up on state during which the wake up control signal is sent to power on the transmitter and the power control signal is sent to power off the transceiver, and wherein the transceiver state machine is configured to:
transition from the full-on state to the full-off state after failing to detect a received data signal for a period determined by a first timing circuit;
transition from the full-off state to the pending wake-up on state after failing to detect a received data signal for an additional period determined by the first timing circuit; and to
transition from the pending wake-up on state to the full-on state after sending out a data link signal, detecting a first received data signal in response to the data link signal within a first period determined by a second timing circuit; and detecting a second received data signal after detecting the first received data signal within a second period determined by the second signal timing circuit.
8. The transceiver power consumption regulator of claim 7 , wherein the transceiver state machine is further configured to transition from the pending wake-up on state to the full-off state after sending out the data link signal and failing to detect a first received data signal within the first period determined by the second timing circuit.
9. The transceiver power consumption regulator of claim 7 , wherein the transceiver state machine is further configured to transition from the pending wake-up on state to the full-off state after sending out the data link signal, detecting the first received data signal in response to the data link signal within the first period determined by the second timing circuit, and failing to detect a second received data signal after detecting the first received data signal within the second period determined by the second signal timing circuit.
10. The transceiver power consumption regulator of claim 7 , wherein the data receiver detects a received data signal by comparing a signal received from the communications network with a reference signal and determining a magnitude of the signal received from the communications network exceeds a magnitude of the reference signal.
11. The transceiver power consumption regulator of claim 7 , wherein the transceiver state machine is further configured to transition from the full-off state to the full-on state after detecting a first received data signal within a period determined by a first timing circuit, waiting for a stand-by period of time determined by a third timing circuit, and detecting a second received data signal after the stand-by period but before a period determined by a fourth data timing circuit.
12. The transceiver power consumption regulator of claim 7 , wherein the transceiver state machine is further configured to remain in the full-off state after detecting a first received data signal within a period determined by a first timing circuit, waiting for a stand-by period determined by a third timing circuit, and failing to detect a second received data signal after the stand-by period but before a period determined by a fourth data timing circuit.