Fabrication method of semiconductor integrated circuit device
View Patent ↗A fabrication method of a semiconductor integrated circuit device comprises, in an SAC process or HARC process, subjecting a semiconductor substrate to plasma etching to make contact holes in an oxide film made of a silicon oxide film formed on the semiconductor substrate. For improving the ease-in-etching property of the silicon oxide film and selectivity to a nitride film, a residence time of an etching gas within a chamber is so set as to be in a range where selectivity to an insulating film made of silicon nitride is improved by using etching conditions of a low pressure and a large flow rate of the etching gas of C 5 H 8 /O 2 /Ar.
1. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:
(a) depositing a silicon oxide insulating film over a patterned silicon nitride film with a doped polycrystalline silicon plug over a semiconductor substrate;
(b) forming a hard mask over said silicon oxide insulating film; and
(c) subjecting said semiconductor substrate to a plasma etching treatment through the hard mask as an etching mask using an etching gas containing a fluorocarbon gas, oxygen and a dilution gas to process said silicon oxide insulating film, so as to form a hole in said silicon oxide insulating film down to the patterned silicon nitride film in such a manner that an upper surface of the doped polycrystalline silicon plug is exposed,
wherein a residence time of the etching gas within an etching chamber is set at 50 to 700 ms.
2. A method according to claim 1 , wherein a pressure within the chamber during the plasma etching ranges from 0.7 to 7 Pa.
3. A method according to claim 1 , wherein a total flow rate of the etching gas passed into the etching chamber ranges from 200 to 1000 cm 3 /minute.
4. A method according to claim 1 , wherein a total flow rate of the etching gas passed into the etching chamber is at 700 cm 3 /minute or over.
5. A method according to claim 1 , wherein a pressure within the etching chamber during the plasma etching ranges from 1.3 to 4 Pa, and the total flow rate of the etching gas passing into the etching chamber is at 700 cm 3 /minute or over.
6. A method according to claim 1 , wherein a flow rate of said dilution gas is larger than the flow rates of said fluorocarbon gas and oxygen.
7. A method according to claim 1 , wherein a plasma density during the plasma etching ranges from 1×10 10 to 1×10 13 /cm 3 .
8. A method according to claim 1 , wherein a plasma density during the plasma etching ranges from 1×10 10 to 1×10 12 /cm 3 .
9. A method according to claim 1 , wherein said fluorocarbon gas is made of C 5 F 8 , and said dilution gas is made of argon.
10. A method according to claim 9 , wherein a flow rate of said argon gas ranges from 200 to 1000 cm 3 /minute.
11. A method according to claim 9 , wherein a flow rate of said argon gas ranges from 400 to 800 cm 3 /minute.
12. A method according to claim 9 , wherein a ratio in flow rate between the oxygen and C 5 F 8 (oxygen/C 5 F 8 ) ranges from 0.8 to 1.5.
13. A method according to claim 9 , wherein a ratio in flow rate between the oxygen and C 5 F 8 (oxygen/C 5 F 8 ) ranges from 1 to 1.2.
14. A method according to claim 9 , wherein a partial pressure of C 5 F 8 ranges from 0.02 to 0.2 Pa.
15. A method according to claim 9 , wherein a partial pressure of C 5 F 8 ranges from 0.04 to 0.1 Pa.
16. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:
(a) depositing a silicon oxide insulating film over a patterned silicon nitride film with a doped polycrystalline silicon plug over a semiconductor substrate;
(b) forming a hard mask over said silicon oxide film; and
(c) subjecting the semiconductor substrate to a plasma etching treatment through the hard mask as an etching mask using an etching gas containing a fluorocarbon gas, oxygen and a dilution gas to process said silicon oxide insulating film, so as to form a hole in said silicon oxide insulating film down to the patterned silicon nitride film in such a manner that an upper surface of the doped polycrystalline silicon plug is exposed,
wherein a residence time of the etching gas within an etching chamber is set at 50 to 350 ms.
17. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:
(a) depositing a silicon oxide insulating film over a patterned silicon nitride film with a doped polycrystalline silicon plug over a semiconductor substrate;
(b) forming a hard mask over said silicon oxide film; and
(c) subjecting the semiconductor substrate to a plasma etching treatment through the hard mask as an etching mask using an etching gas containing a fluorocarbon gas, oxygen and a dilution gas to process said silicon oxide insulating film, so as to form a hole in said silicon oxide insulating film down to the patterned silicon nitride film in such a manner that an upper surface of the doped polycrystalline silicon plug is exposed,
wherein a residence time of the etching gas within an etching chamber is set at 100 to 200 ms.
18. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:
(a) depositing a silicon oxide insulating film over a patterned silicon nitride film with a doped polycrystalline silicon plug over a semiconductor substrate;
(b) forming a hard mask over said silicon oxide film: and
(c) subjecting the semiconductor substrate to a plasma etching treatment through the hard mask as an etching mask using an etching gas containing a fluorocarbon gas, oxygen and a dilution gas to process said silicon oxide insulating film, so as to form a hole in said silicon oxide insulating film down to the patterned silicon nitride film in such a manner that an upper surface of the doped polycrystalline silicon plug is exposed,
wherein a pressure within the etching chamber during the plasma etching ranges from 0.7 to 7 Pa and a total flow rate of the etching gas passed into the etching chamber is 700 cm 3 /minute or over.
19. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:
(a) depositing a silicon oxide insulating film over a patterned silicon nitride film with a doped polycrystalline silicon plug over a semiconductor substrate;
(b) forming a hard mask over said silicon oxide film; and
(c) subjecting the semiconductor substrate to a plasma etching treatment through the hard mask as an etching mask using an etching gas containing a fluorocarbon gas, oxygen and a dilution gas to process said silicon oxide insulating film, so as to form a hole in said silicon oxide insulating film down to the patterned silicon nitride film in such a manner that an upper surface of the doped polycrystalline silicon plug is exposed,
wherein a pressure within the etching chamber during the plasma etching ranges from 1.3 to 4 Pa and a total flow rate of the etching gas passed into the etching chamber is 700 cm 3 /minute or over.