IP Library Granted Patent US 7,178,145
Granted Patent B2
US 7,178,145 · App. 09/896,860 · Granted Feb 13, 2007

Queues for soft affinity code threads and hard affinity code threads for allocation of processors to execute the threads in a multi-processor system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,178,145
App. No.
09/896,860
Granted
Feb 13, 2007
Kind
B2
Abstract

In a multi-processor system, each processor has a respective hard affinity queue and soft affinity queue. For execution of a thread, a queue loader places an instance of the thread upon the hard or soft affinity queue of a selected processor. The selection may use an affinity attribute, processor attribute, accessor function, or a respective program of code threads for each processor. A thread instance on a processor's hard affinity queue is executed only by that processor. A thread instance on a processor's soft affinity queue is executed by that processor unless another processor has a soft affinity queue empty of thread instances ready for execution. Each processor alternates service priority between its hard and soft affinity queues. When a thread has a soft affinity it is initially bound to the processor it is started from. It will, then, be bound to the last processor it has been run on.

Claims (54)

1. A method of distributing and executing instances of code threads in a multi-processor system having a plurality of processors, said method comprising:

assigning a respective one of the processors to each code thread instance, and assigning either a hard affinity or a soft affinity to said each code thread instance so that said each code thread instance is either a hard affinity code thread instance or a soft affinity code thread instance;

the processor assigned to each hard affinity code thread instance executing said each hard affinity code thread instance; and

the processor assigned to each soft affinity code thread instance executing said each soft affinity code thread instance unless said each soft affinity code thread instance is ready and waiting for execution when another processor has no assigned soft affinity code thread instance ready and waiting for execution and said another processor finds that said each soft affinity code thread instance is ready and waiting for execution so that said another processor executes said each soft affinity code thread instance.

2. The method as claimed in claim 1 , wherein the assigning of either a hard affinity or a soft affinity to said each code thread instance includes decoding an affinity attribute of the code thread of said each code thread instance, the affinity attribute providing information regarding assignment of either a hard affinity or a soft affinity to said each code thread instance.

3. The method as claimed in claim 1 , which includes assigning a plurality of code threads to at least one of the processors by including the plurality of code threads in a respective program for said at least one of the processors to execute.

4. The method as claimed in claim 3 , which includes said at least one of the processors executing the respective program for said at least one of the processors to load instances of code threads of the respective program onto either a queue of hard affinity code thread instances for said at least one of the processors or a queue of soft affinity code thread instances for said at least one of the processors.

5. The method as claimed in claim 1 , wherein at least one of the code threads contains a processor attribute identifying the respective one of the processors to be assigned to instances of said at least one of the code threads, and the method includes obtaining the processor attribute from said at least one of the code threads to assign the respective one of the processors to at least one instance of said at least one of the code threads.

6. The method as claimed in claim 1 , wherein at least one of the code threads includes a function to be evaluated for determining the respective one of the processors to be assigned to instances of said at least one of the code threads, and the method further includes evaluating the function to determine the respective one of the processors to assign to at least one instance of said at least one of the code threads.

7. The method as claimed in claim 6 , wherein the multi-processor system includes a number of the processors, the function is a hashing function, and the evaluation of the hashing function includes computing a remainder of an integer division by the number of the processors so that the remainder indicates the respective one of the processors to assign to said at least one instance of said at least one of the code threads.

8. The method as claimed in claim 1 , which includes assigning a respective instance of a hard affinity monitor or debug code thread to each of the processors so that each of the processors executes the respective instance of the hard affinity monitor or debug code thread issued to each of the processors to monitor or debug a function executed by any of the processors.

9. The method as claimed in claim 1 , which includes assigning a respective instance of a hard affinity watchdog code thread to each of the processors so that each of the processors executes the respective instance of the hard affinity watchdog code thread to detect improper operation of said each of the processors.

10. The method as claimed in claim 1 , which includes issuing a respective instance of a hard affinity code thread to each of the processors so that each of the processors executes the respective instance of the hard affinity code thread issued to each of the processors.

11. The method as claimed in claim 1 , which includes responding to a request of a client in a data processing network by assigning, to an instance of a client manager code thread, a processor selected by hashing at least a portion of a client identifier associated with the client request.

12. The method as claimed in claim 1 , which includes responding to a file access request for access to a specified file system by assigning, to an instance of a file system manager code thread, a processor having been pre-assigned to process requests for access to the specified file system.

13. A method of distributing and executing code thread instances in a multi-processor system having a plurality of processors, each of the processors having a respective hard affinity queue and a respective soft affinity queue, said method comprising:

placing each of the code thread instances on either the hard affinity queue or the soft affinity queue of a respective one of the processors; and

each of the processors servicing the hard affinity queue of said each of the processors so that each code thread instance having been placed on the hard affinity queue of said each of the processors is not executed by any processor other than said each of the processors, said each of the processors servicing the soft affinity queue of said each of the processors and also another one of the processors servicing the soft affinity queue of said each of the processors but at a lower priority than said another one of the processors services the soft affinity queue of said another one of the processors.

14. The method as claimed in claim 13 , wherein at least one of the processors services the soft affinity queue of said at least one of the processors by executing a next code thread instance on the soft affinity queue of said at least one of the processors when the soft affinity queue of said at least one of the processors is not empty of code thread instances ready for execution, and when the soft affinity queue of said at least one of the processors is empty of code thread instances ready for execution, servicing the soft affinity queue of at least one of the other processors.

15. The method as claimed in claim 14 , wherein said at least one of the processors services the soft affinity queue of the other processors by inspecting the soft affinity queues of the other processors in a numerical sequence of the other processors until a soft affinity queue is found that is not empty of code thread instances ready for execution and a code thread is obtained from the soft affinity queue that is found to be not empty of code thread instances ready for execution or until all of the soft affinity queues of the other processors in the system are found to be empty of code thread instances ready for execution.

16. The method as claimed in claim 13 , which includes decoding an affinity attribute of a code thread, the affinity attribute providing information regarding whether to place an instance of the code thread upon either a hard affinity queue or a soft affinity queue.

17. The method as claimed in claim 13 , which includes producing a program of code threads for said each of the processors, and placing instances of the code threads of the program of code threads for said each of the processors on the hard affinity queue or soft affinity queue of said each of the processors.

18. The method as claimed in claim 13 , wherein a code thread contains a processor attribute indicating the respective one of the processors having a hard or soft affinity queue upon which instances of the code thread should be placed, and the method includes obtaining the processor attribute from the code thread and placing at least one instance of the code thread on the hard or soft affinity queue of the respective one of the processors indicated by the affinity attribute obtained from the code thread.

19. The method as claimed in claim 13 , wherein a code thread contains a function to be evaluated for determining the respective one the processors having an affinity queue upon which instances of the code thread should be placed, and the method includes evaluating the function to determine the respective one of the processors having an affinity queue upon which an instance of the code thread should be placed.

20. The method as claimed in claim 19 , wherein the multi-processor system includes a number of the processors, the function is a hashing function, and the evaluation of the function includes computing a remainder of an integer division by the number of the processors to produce a remainder indicating the respective one of the processors having a hard or soft affinity queue upon which the instance of the code thread should be placed.

21. The method as claimed in claim 13 , which includes assigning a respective instance of a hard affinity monitor or debug code thread to said each of the processors so that said each of the processors executes the respective instance of the hard affinity monitor or debug code thread issued to said each of the processors to monitor or debug a function executed by any of the processors.

22. The method as claimed in claim 13 , which includes assigning a respective instance of a hard affinity watchdog code thread to said each of the processors so that said each of the processors executes the respective instance of the hard affinity watchdog code thread to detect improper operation of said each of the processors.

23. The method as claimed in claim 13 , which includes placing a respective instance of a code thread upon the hard affinity queue of said each of the processors so that said each of the processors executes a respective instance of the code thread placed upon the hard affinity queue of said each of the processors.

24. The method as claimed in claim 13 , which includes responding to a client request by hashing at least a portion of a client identifier associated with the client request in order to obtain an identification of one of the processors having a hard affinity queue onto which is placed an instance of a client manager code thread for processing the client request.

25. The method as claimed in claim 13 , which includes responding to a request for access to a specified file system by placing an instance of a file system manager thread upon the hard affinity queue of one of the processors having been pre-assigned to process requests for access to the specified file system.

26. A multi-processor system comprising memory and a plurality of processors coupled to the memory for access to the memory, each of the processors having a respective hard affinity queue and a respective soft affinity queue, the queues indicating code thread instances waiting for execution, said each of the processors being programmed for servicing the hard affinity queue of said each of the processors so that each code thread instance having been placed on the hard affinity queue of said each of the processors is not executed by any processor other than said each of the processors, said each of the processors being programmed for servicing the soft affinity queue of said each of the processors and also another one of the processors being programmed for servicing the soft affinity queue of said each of the processors at a lower priority than the soft affinity queue of said another one of the processors.

27. The multi-processor system as claimed in claim 26 , wherein at least one of the processors is programmed to periodically interrupt execution of a current code thread instance by said at least one of the processors to determine whether or not execution of the current code thread instance should be suspended to execute another code thread instance having higher execution priority than the current code thread instance, and wherein said at least one of the processors alternates service priority between servicing the hard affinity queue of said at least one of the processors and servicing the soft affinity queue of said at least one of the processors.

28. The multi-processor system as claimed in claim 26 , wherein at least one of the processors is programmed for servicing the soft affinity queue of said at least one of the processors by executing a next code thread instance on the soft affinity queue of said at least one of the processors when the soft affinity queue of said at least one of the processors is not empty of code thread instances ready for execution, and when the soft affinity queue of said at least one of the processors is empty of code thread instances ready for execution, servicing the soft affinity queue of at least one of the other processors.

29. The multi-processor system as claimed in claim 28 , wherein said at least one of the processors is programmed for servicing the soft affinity queue of the other processors by inspecting the soft affinity queues of the other processors in a numerical sequence of the other processors until a soft affinity queue is found that is not empty of code thread instances ready for execution and a code thread is obtained from the soft affinity queue that is found to be not empty of code thread instances ready for execution or until all of the soft affinity queues of the other processors in the system are found to be empty of code thread instances ready for execution.

30. The multi-processor system as claimed in claim 26 , wherein at least one of the processors is programmed for placing code thread instances on the hard and soft affinity queues by decoding an affinity attribute of a code thread, the affinity attribute providing information regarding whether to place an instance of the code thread upon either a hard affinity queue or a soft affinity queue.

31. The multi-processor system as claimed in claim 26 , which includes a respective program for said each of the processors, the respective program containing hard and soft affinity code threads assigned to said each of the processors.

32. The multi-processor system as claimed in claim 26 , wherein a code thread contains a processor attribute indicating the respective one of the processors having a hard or soft affinity queue upon which instances of the code thread should be placed, and at least one of the processors is programmed for obtaining the processor attribute from the code thread and placing at least one instance of the code thread on the hard or soft affinity queue of the respective one of the processors indicated by the affinity attribute obtained from the code thread.

33. The multi-processor system as claimed in claim 26 , wherein a code thread contains a function to be evaluated for determining the respective one the processors having a hard or soft affinity queue upon which instances of the code thread should be placed, and at least one of the processors is programmed for evaluating the function to determine the respective one of the processors having a hard or soft affinity queue upon which an instance of the code thread should be placed.

34. The multi-processor system as claimed in claim 33 , wherein the multi-processor system includes a number of the processors, the function is a hashing function, and the evaluation of the function includes computing a remainder of an integer division by the number of the processors to produce a remainder indicating the respective one of the processors having a hard or soft affinity queue upon which the instance of the code thread should be placed.

35. The multi-processor system as claimed in claim 26 , wherein at least one of the processors is programmed for placing a monitor or debug code thread instance on the hard affinity queue of each of the processors to monitor or debug a function executed by any of the processors.

36. The multi-processor system as claimed in claim 26 , wherein at least one of the processors is programmed for placing a hard affinity watchdog code thread instance on the hard affinity queue of said each of the processors so that said each of the processors executes the respective instance of the hard affinity watchdog code thread to detect improper operation of any of the processors.

37. The multi-processor system as claimed in claim 26 , wherein at least one of the processors is programmed for placing a respective instance of a code thread upon the hard affinity queue of said each of the processors so that said each of the processors executes a respective instance of the code thread placed upon the hard affinity queue of said each of the processors.

38. The multi-processor system as claimed in claim 26 , wherein the multi-processor system is part of a network server, and at least one of the processors is programmed for responding to a client request by hashing at least a portion of a client identifier associated with the client request in order to obtain an identification of one of the processors having a hard affinity queue onto which is placed an instance of a client manager code thread for processing the client request.

39. The multi-processor system as claimed in claim 26 , wherein the multi-processor system is part of a file server, and at least one of the processors is programmed for responding to a request for access to a specified file system by placing an instance of a file system manager code thread upon the hard affinity queue of one of the processors having been pre-assigned to process requests for access to the specified file system.

40. A multi-processor system having multiple processors and a shared memory coupled to the processors for access to the shared memory, the shared memory containing memory-resident code threads, a queue loader routine for queuing code thread instances, a queue service routine for dispatching code thread instances to the processors for execution, and a code thread manager program using the queue loader routine, wherein the multi-processor system further comprises:

each of the processors having a respective hard affinity queue contained in the shared memory and a respective soft affinity queue contained in the shared memory;

the queue loader routine being executable for loading each code thread instance onto a selected soft or hard affinity queue of a selected one of the processors;

the queue service routine being executable by each of the processors for servicing the hard and soft affinity queues of said each of the processors and for servicing the soft affinity queues of the other processors when the soft affinity queue of said each of the processors is empty of code thread instances ready for execution; and

wherein the queue service routine is executable for servicing the soft affinity queues of the processors by executing a next code thread instance on the soft affinity queue of the processor executing the queue service routine when the soft affinity queue of said at least one of the processors is not empty of code thread instances ready for execution, and when the soft affinity queue of the processor executing the queue service routine is empty of code thread instances ready for execution, servicing the soft affinity queues of the other processors.

41. The multi-processor system as claimed in claim 40 , wherein the queue service routine is executable for servicing the soft affinity queues of the other processors by inspecting the soft affinity queues of the other processors in a numerical sequence of the other processors until a soft affinity queue is found that is not empty of code thread instances ready for execution and a code thread is obtained from the soft affinity queue that is found to be not empty of code thread instances ready for execution or until all of the soft affinity queues of the other processors are found to be empty of code thread instances ready for execution.

42. The multi-processor system as claimed in claim 40 , wherein a code thread contains a function to be evaluated for determining a respective one the processors having a hard or soft affinity queue upon which instances of the code thread should be placed, and the queue loader routine is executable for evaluating the function to determine the respective one of the processors having a hard or soft affinity queue upon which an instance of the code thread should be placed.

43. The multi-processor system as claimed in claim 42 , wherein the multi-processor system includes a number of the processors, the function is a hashing function, and the evaluation of the function includes computing a remainder of an integer division by the number of the processors to produce a remainder indicating the respective one of the processors having a hard or soft affinity queue upon which the instance of the code thread should be placed.

44. The multi-processor system as claimed in claim 40 , wherein the queue loading routine is executable for decoding an affinity attribute of a code thread, the affinity attribute providing information regarding whether to place an instance of the code thread upon either a hard affinity queue or a soft affinity queue.

45. The multi-processor system as claimed in claim 40 , wherein a code thread contains a processor attribute indicating a respective one of the processors having a hard or soft affinity queue upon which instances of the code thread should be placed, and the queue loader routine is executable for obtaining the processor attribute from the code thread and placing at least one instance of the code thread on the hard or soft affinity queue of the respective one of the processors indicated by the affinity attribute obtained from the code thread.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →