Granted Patent
Utility
US 6,351,432
· Confirmation No. 6056
Synchronous semiconductor memory apparatus and input information latch control method thereof
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-07-16 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-07-16 | SPEC |
Specification | 31 | View | |
| 2001-07-16 | CLM |
Claims | 5 | View | |
| 2001-07-16 | ABST |
Abstract | 1 | View | |
| 2001-07-16 | DRW |
Drawings-only black and white line drawings | 14 | View | |
| 2001-07-16 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Mitsuhiro Higashiho
Kasugai, JAPAN
Shigemasa Ito
Kasugai, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/189.05
Prosecution
- Examiner
- TRAN, ANDREW Q
- Art Unit
- 2824
- Docket No.
- 024016-00009
- Confirmation No.
- 6056
Foreign Priority
2000-266889
·
2000-09-04
·
JAPAN
Publication
- Pub. No.
- US20020027829A1
- Pub. Date
- 2002-03-07
Patent Term Adjustment
-91days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-04-27
CHANGE OF NAME
Recorded 2010-07-22
from
FUJITSU LIMITED
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2008-12-12
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-07-16
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Quick Facts
- Patent No.
- US 6,351,432
- App. No.
- 09/904,479
- Filed
- 2001-07-16
- Granted
- 2002-02-26
- Pub. No.
- US20020027829A1
- Examiner
- TRAN, ANDREW Q
- Art Unit
- 2824
- PTA
- -91 days
External Links