System and method to avoid resource contention in the presence of exceptions
View Patent ↗A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction has an associated status bit, which is set if the instruction excepts. Each excepting instruction is logged in an exception logging unit, which causes the associated status bit to be set. Each program has an associated in-flight vector table that tracks the instructions that have been fetched for that program. The status bits are compared with the in-flight vector table to identify the program that is associated with an excepted instruction. That program is then disabled, thereby preventing further fetching of instructions for that program until the excepted instruction clears.
1. A multi-threaded processor, comprising;
a plurality of thread processing units capable of concurrently processing one or more instructions from different programs;
a fetching unit that fetches instructions for each of said plurality of thread processing units;
a non-speculative exception handler that receives an indication of any of a first group of excepting speculative instructions, and identifies the program associated with said excepted instruction, and wherein said exception handler generates a signal to said fetching unit to disable fetching for the program associated with the excepted instruction until the processor determines that the excepted instruction is associated with an actual program path, and permitting the fetching unit to continue fetching instructions for at least one other thread processing unit so that processor resources can continue to be used to execute instructions such at least one other program running on another thread processing unit; and
a speculative exception handler that receives an indication of any of a second group of excepting speculative instructions and, without the processor determining whether a second group instruction is from the actual program path, the speculative exception handler resolves said second group excepted instruction.
2. The processor of claim 1 , wherein the non-speculative exception handler includes a wi a plurality of status bits, and wherein each status bit corresponds to a particular instruction fetched by said fetching unit.
3. The processor of claim 2 , wherein the non-speculative exception handler also includes an in-flight vector table for each of said plurality of thread processing units, and wherein each in-flight vector table comprises a map that includes a bit corresponding to each instruction fetched said fetching unit, and wherein the bits in said map are set that correspond to program instructions executed by the associated thread processing unit.
4. The processor of claim 3 , further comprising a comparator associated with each in-flight vector table that compares each of said status bits with the corresponding map bit in the in-flight vector table.
5. The processor of claim 4 , wherein each of the thread processing units is capable of processing a different program.
6. The multi-threaded processor of claim 1 wherein the first group of excepting speculative instructions comprise instructions selected from a group consisting of instructions that cannot be decoded, instructions that result in a divide by zero condition, arithmetic overflows, and cache parity errors.
7. The multi-threaded processor of claim 6 wherein the second group of excepting speculative instructions comprises exceptions selected from the group consisting of branch mispredictions, jump mispredictions, and load/store order traps.
8. The multi-threaded processor of claim 1 wherein the second group of excepting speculative instructions comprises exceptions selected from the group consisting of branch mispredictions, jump mispredictions, and load/store order traps.
9. A method of handling exceptions in a processor during the execution of a plurality of programs, comprising:
detecting an exception for a speculative instruction in one or more stages of one or more pipelines;
determining whether to defer resolution, of said exception based on an exception type for said excepted speculative instruction;
after determining whether to defer resolution of said exception, determining whether said excepted speculative instruction needs to be executed;
discontinuing fetching of instructions associated with a speculative instruction whose exception is of a type that is determined not be critical to processor performance permitting other thread processing units in said processor to use processor resources to execute instructions; and
routing at least some of said detected exceptions to a first exception handler and some of said detected exceptions to a second exception handler.
10. The method of claim 9 , further comprising not deferring resolution of said exception if said exception type is critical to processor performance.
11. The method of claim 10 , further comprising continuing fetching instructions upon resolution of said exception.
12. The method of claim 11 , wherein said first exception handler identifies the program that is the source of the excepted instruction.
13. A processor capable of executing multiple programs, comprising:
a plurality of thread processing; units capable of executing one or more instructions from different programs;
a fetching unit that fetches instructions for said thread processing units;
logic that includes a non-speculative exception handler and a speculative exception handler, the logic detects exceptions to speculative instructions and defers processing of some of said exceptions, but not other of said exceptions; and
fetch logic that fetches instructions for said thread processing units and that is disabled from fetching instructions for one of said thread procession units upon detection of an exception, the processing of which is to be deferred, wherin the fetch is disabled from fetching instructions for said one of said thread processing units until said deterred exception is eventually processed, but continues to execute instructions in said other thread processing units.
14. The processor of claim 13 wherein, whether the logic defers processing of some of said exceptions, but not other of said exceptions, depends on exception type.
15. The processor of claim 14 wherein a first exception type that causes the logic to defer processing comprises branch mispredictions, jump mispredictions, and load/store order traps.
16. The processor of claim 15 wherein a second exception type that causes the logic to defer processing comprises instructions selected from a group consisting of instructions that cannot be decoded, instructions that result in a divide by zero condition, arithmetic overflows, and cache parity errors.
17. The processor of claim 14 wherein an exception type that causes the logic not to defer processing comprises instructions selected from a group consisting of instructions that cannot be decoded, instructions that result in a divide by zero condition, arithmetic overflows, and cache parity errors.
18. An exception handler that resolves excepted speculative instructions within a processor comprising:
a first exception handler unit that begins to resolve a first type of exception without determining whether the instructions associated with said first type of exceptions need to be executed; and
a second exception handler unit that defers resolution of a second type of exception until it is determined that the instructions associated with said second type of exception need to be executed and disables a fetch logic from fetching additional instructions for a thread processing unit containing an excepted instruction of the second type but permitting said fetch logic to continue fetching instructions for another thread processing unit.
19. The exception handler of claim 18 wherein the first type of exception comprises exceptions selected from the group consisting of branch mispredictions, jump mispredictions, and load/store order traps.
20. The exception handler of claim 18 wherein the second type of exception comprises exceptions selected from the group consisting of instructions that cannot be decoded, instructions that result in a divide by zero condition, arithmetic overflows, and cache parity errors.
21. The exception handler of claim 18 wherein the first type of exception comprises critical exceptions and the second type of exception comprises non-critical exceptions.