Disabling a clock signal to a peripheral interface engine block during peripheral operation in a selected operational mode

1. A method for operating a peripheral device having at least two operational modes, the method comprising:

selecting a first one of the at least two operational modes for the peripheral device;

supplying a first clock signal to a first interface engine block associated with the first one of the at least two operational modes; and

disabling a second clock signal to a second interface engine block associated with a second one of the at least two operational modes.

2. The method of claim 1 , wherein selecting the first one of the at least two operational modes comprises:

sending a first signal to a host device that indicates that the peripheral device is operable in the first one of the at least two operational modes; and

receiving a second signal from the host device that indicates that the host device supports the first one of the at least two operational modes.

3. The method of claim 1 , wherein the peripheral device comprises a USB 2.0 device, and

wherein the at least two operational modes comprise a low speed operational mode, a full speed operational mode, and a high speed operational mode.

4. The method of claim 3 , wherein the first one of the at least two operational modes comprises the high speed operational mode,

wherein the first interface engine block comprises a parallel interface engine block, and

wherein

the second interface engine block comprises a serial interface engine block.

5. The method of claim 4 , wherein the first one of the at least two operational modes comprises one of the low speed operational mode and the full speed operational mode,

wherein the first interface engine block comprises a serial interface engine block, and

wherein the second interface engine block comprises a parallel interface engine block.

6. The method of claim 1 , wherein selecting the first one of the at least two operational modes comprises:

sending a first signal to a host device that indicates that the peripheral device is operable in a second one of the at least two operational modes; and

selecting the first one of the at least two operational modes after non-receipt, within a prescribed time period, of a second signal from the host device that indicates that the host device supports the second one of the at least two operational modes.

7. A system comprising:

a first interface engine block;

a second interface engine block;

a speed enumeration block for selecting one of a first operational mode and a second operational mode for the system; and

clock gating logic for providing a first clock signal to the first interface engine block and disabling a second clock signal for the second interface engine block during the first operational mode, and for disabling the first clock signal for the first interface engine block and providing the second clock signal to the second interface engine block during the second operational mode.

8. The system of claim 7 , wherein the speed enumeration block comprises:

a first logic component for sending a first signal to a host device, the first signal indicating that the system is operable in one of the first operational mode and the second operational mode; and

a second logic component for receiving a second signal from the host device, the second signal indicating that the host device supports the one of the first operational mode and the second operational mode for the system.

9. The system of claim 7 , wherein the system comprises a USB 2.0 peripheral, and

wherein the first interface engine block and the second interface engine block comprise a serial interface engine block and a parallel interface engine block, respectively.

10. The system of claim 9 , wherein the first operational mode comprises one of a low speed operational mode and a full speed operational mode, and

wherein the second operational mode comprises a high speed operational mode.

11. The system of claim 7 , wherein the speed enumeration block comprises:

a first logic component for sending a first signal to a host device, the first signal identifying the system as being functional in a first one of the first operational mode and the second operational mode; and

a second logic component for selecting a second one of the first operational mode and the second operational mode after non-receipt, within a prescribed time period, of a second signal from the host device, the second signal indicating support by the host device for the first one of the first operational mode and the second operational mode.

12. A device for controlling clock signals to a serial interface engine block (SIE) and a parallel interface engine block (PIE) in a USB 2.0 peripheral, the device comprising:

clock gating logic for providing a first clock signal to the SIE and disabling a second clock signal to the PIE when the USB 2.0 peripheral operates in one of a low speed operational mode and a full speed operational mode, and for disabling the first clock signal to the SIE and providing the second clock signal to the PIE

when the USB 2.0 peripheral operates in a high speed operational mode.