Patent Application
Utility
App. No. 09/907,675
· Confirmation No. 9349
SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF INTERCONNECTION LAYERS, MANUFACTURING METHOD THEREOF AND METHOD OF DESIGNING SEMICONDUCTOR CIRCUIT USED IN THE MANUFACTURING METHOD
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-07-19 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-07-19 | SPEC |
Specification | 34 | View | |
| 2001-07-19 | CLM |
Claims | 6 | View | |
| 2001-07-19 | ABST |
Abstract | 1 | View | |
| 2001-07-19 | DRW |
Drawings-only black and white line drawings | 16 | View | |
| 2001-07-19 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Hiroyuki Amishiro
Hyogo, JAPAN
Motoshige Igarashi
Hyogo, JAPAN
Attorneys & Agents of Record
Classification
USPC
257/751
H10W20/435
H10W20/495
Prosecution
- Examiner
- QUACH, TUAN N
- Art Unit
- 2814
- Docket No.
- 57454-152
- Confirmation No.
- 9349
Foreign Priority
11-014070(P)
·
1999-01-22
·
JAPAN
Publication
- Pub. No.
- US20020024141A1
- Pub. Date
- 2002-02-28
Patent Term Adjustment
0days
No recorded assignments were found for this patent.
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Quick Facts
- App. No.
- 09/907,675
- Filed
- 2001-07-19
- Granted
- 2003-04-01
- Pub. No.
- US20020024141A1
- Examiner
- QUACH, TUAN N
- Art Unit
- 2814
- PTA
- 0 days
External Links