Method and system for turbo encoding in ADSL
View Patent ↗In a coding system for asymmetric digital subscriber line (ADSL) communications, a method of encoding a sequence of information bits is provided comprising the steps of dividing the information bits into encoding bits and parallel bits; encoding the encoding bits to produce encoded bits; mapping the encoded bits and the parallel bits into first and second pulse amplitude modulation (PAM) signals; and generating a quadrature amplitude modulation (QAM) signal from these first and second PAM signals. This method overcomes the decoder complexity that would otherwise be required due to the large QAM constellations involved for ADSL communications.
1. A method of encoding a sequence of information bits in a communication system comprising:
dividing said sequence of information bits into encoding bits and parallel bits;
encoding said encoding bits to produce encoded bits;
mapping said encoded bits and said parallel bits into first and second pulse amplitude modulation (PAM) signals;
generating a quaternary amplitude modulation (QAM) signal from said first and said second PAM signals; and
identifying whether a number of said information bits is odd or even;
wherein said mapping is a concatenated Gray mapping; and
said concatenated Gray mapping is a serial concatenation of an inner Gray mapping and an outer Gray mapping.
2. The method of claim 1 , further comprising:
transmitting said QAM signal from said communication system associated with said method of encoding.
3. The method of claim 2 , wherein said communication system is an asymmetric digital subscriber line (ADSL) communication system.
4. The method of claim 1 , comprising:
selecting a mode of operation based on an odd or even status of said number of said information bits.
5. The method of claim 4 , wherein said mode of operation determines a number of said encoding bits, a puncture pattern used in said encoding, a coding rate used in said encoding, and a number of said encoded bits and said parallel bits used in said mapping.
6. The method of claim 4 , wherein said selecting is made between a first mode of operation and a second mode of operation.
7. The method of claim 1 , wherein if a number of said information bits is even, a number of said encoding bits is two.
8. The method of claim 1 , wherein if a number of said information bits is even, a number of said coding bits is greater than two.
9. The method of claim 1 , wherein if a number of said information bits is odd, a number of said encoding bits is three.
10. The method of claim 1 , wherein if a number of said information bits is odd, a number of said coding bits is greater than three.
11. The method of claim 1 , wherein said encoded bits consist of systematic bits and parity bits.
12. The method of claim 11 , wherein if a number of said information bits is even, a number of said systematic bits is two and a number of said parity bits is two.
13. The method of claim 11 , wherein if a number of said information bits is odd, a number of said systematic bits is three and a number of said parity bits is one.
14. The method of claim 1 , wherein said encoding is performed by a turbo encoder.
15. The method of claim 1 , wherein said encoding is performed by multiple turbo encoders.
16. The method of claim 1 , wherein said encoding is performed by a serial concatenated turbo encoder.
17. The method of claim 1 , wherein said encoding is performed by a turbo product code encoder.
18. The method of claim 1 , wherein said encoding is performed by an low density parity check (LDPC) encoder.
19. The method of claim 1 , wherein said mapping includes:
forming a first vector and a second vector from said encoded bits and said parallel bits.
20. The method of claim 19 , wherein said mapping further includes:
mapping said first vector to said first PAM signal and mapping said second vector to said second PAM signal.
21. The method of claim 19 , wherein each of said first and said second vectors is formed from alternate ones of said encoded bits and said parallel bits.
22. The method of claim 21 , wherin said alternate ones of said encoded bits form least significant bits and said alternate ones of said parallel bits form most significant bits of each of said first and said second vectors.
23. A method of encoding a sequence of information bits in a communication system comprising:
dividing said sequence of information bits into encoding bits and parallel bits;
encoding said encoding bits to produce encoded bits;
mapping said encoded bits and said parallel bits into first and second pulse amplitude modulation (PAM) signals; and
generating a quaternary amplitude modulation (QAM) signal from said first and said second PAM signals; and
wherein said mapping is a concatenated Gray mapping; and
said concatenated Gray mapping is a serial concatenation of an inner Gray mapping and an outer Gray mapping.
24. The method of claim 23 , wherein said inner Gray mapping is applied to said encoded bits and said outer Gray mapping is applied to said parallel bits.
25. An apparatus for encoding a sequence of bits in an asymmetric digital subscriber line (ADSL) system, comprising:
a plurality of signal lines configured to divide said sequence of information bits into encoding bits and parallel bits;
at least one turbo encoder configured to encode said encoding bits to produce encoded bits; and
a quaternary amplitude modulation (QAM) unit configured to map said encoded bits and said parallel bits into first and second pulse amplitude modulation (PAM) signals and to generate a QAM signal from said first and said second PAM signals; and
a control unit configured to identify whether a number of said information bits is odd or even.
26. The apparatus of claim 25 , wherein said control unit is further configured to generate a mode control signal based on an odd or even status of said number of information bits.
27. The apparatus of claim 26 , wherein said mode control signal is provided to said at least one turbo encoder and said QAM unit to determine a number of said encoding bits, a puncture pattern used in said encoding, a coding rate used in said encoding, and a number of said encoded bits and said parallel bits used in said mapping.
28. The apparatus of claim 25 , wherein if a number of said information bits is even, a number of said encoding bits is two.
29. The apparatus of claim 25 , wherein if a number of said information bits is even, a number of said coding bits is greater than two.
30. The apparatus of claim 25 , wherein if a number of said information bits is odd, a number of said encoding bits is three.
31. The apparatus of claim 25 , wherein if a number of said information bits is odd, a number of said coding bits is greater than three.
32. The apparatus of claim 25 , wherein said encoded bits consist of systematic bits and parity bits.
33. The apparatus of claim 32 , wherein if a number of said information bits is even, a number of said systematic bits is two and a number of said parity bits is two.
34. The apparatus of claim 32 , wherein if a number of said information bits is odd, a number of said systematic bits is three and a number of said parity bits is one.
35. The apparatus of claim 25 , wherein said at least one turbo encoder comprises at least one serial concatenated turbo encoder.
36. The apparatus of claim 25 , wherein said at least one turbo encoder comprises at least one turbo product code encoder.
37. The apparatus of claim 25 , wherein said at least one turbo encoder comprises a low density parity check (LDPC) encoder.
38. The apparatus of claim 25 , wherein said QAM unit is further configured to form a first vector and a second vector from said encoded bits and said parallel bits.
39. The apparatus of claim 38 , wherein said QAM unit is further configured to map said first vector to said first PAM signal and mapping said second vector to said second PAM signal.
40. The apparatus of claim 38 , wherein said QAM unit is further configured to form each of said first and said second vectors from alternate ones of said encoded bits and said parallel bits.
41. The apparatus of claim 40 , wherein said QAM unit is further configured to use said alternate ones of said encoded bits to form least significant bits and said alternate ones of said parallel bits to form most significant bits of each of said first and said second vectors.
42. The apparatus of claim 25 , wherein said QAM unit is further configured to use a concatenated Gray mapping to map said encoded bits and said parallel bits.
43. The apparatus of claim 42 , wherein said QAM unit is further configured to implement said concatenated Gray mapping as a serial concatenation of an inner Gray mapping and an outer Gray mapping.
44. The apparatus of claim 43 , wherein said QAM unit is further configured to apply said inner Gray mapping to said encoded bits and said outer Gray mapping to said parallel bits.