Method and circuit for picture-in-picture superimposition

1. A method for picture-in-picture insertion, in which a sequence of decimated inset pictures is written to a memory device and is read out for insertion into a sequence of main pictures, the method comprising the steps of:

writing inset pictures to the memory device in a circulating manner as fields under continuously incremented write addresses, the inset pictures being written to corresponding memory segments beginning at corresponding writing start addresses,

storing the writing start address of each written-in field,

each time the write address is incremented, by comparison of the respective instantaneous write address with a previously stored writing start address, an overtake signal, which indicates whether the respective writing start address is reached again and the memory segment corresponding to the respective writing start address is overwritten,

by evaluation of the overtake signal, selecting for read out the memory segment corresponding to the last writing start address stored or the penultimate writing start address stored, and

reading out the selected memory segment for insertion into the respective main picture with continuously incremented read addresses.

2. The method of claim 1 further comprising continuously incrementing the write and read addresses from a first memory address up to a last memory address and are in each case resetting the write and read addresses to the first memory address again after the last memory address has been reached.

3. The method of claim 1 further comprising, in order to insert an inset picture into a main picture, in each case storing the picture position and size are in the form of a number of lines and also pixels per line in a segment buffer for two inset pictures.

4. The method of claim 1 further comprising effecting the raster correction by comparison between the raster position of a picture to be displayed and the raster position of a stored picture and also by skipping or repeating a line.

5. The method of claim 1 further comprising, each time the write address is incremented, comparing the instantaneous write address with the penultimate writing start address stored wherein, in the event of correspondence, the last writing start address stored is used as reading start address for reading the corresponding memory segment, whereas otherwise the penultimate writing start address is used as reading start address for reading the corresponding memory segment.

6. A circuit arrangement for inserting a sequence of decimated inset pictures into a sequence of main pictures, comprising:

a write controller for writing the inset pictures as fields under continuously incremented write addresses to corresponding memory segments of a memory device beginning at corresponding writing start addresses,

having a segment buffer for storing the writing start address of each field written to the memory device, in which case an overtake signal can be generated by the write controller each time the write address is incremented, by comparing the respective instantaneous write address with a previously stored writing start address, which overtake signal indicates whether the respective writing start address is reached again and the memory segment of the memory device which corresponds to the respective writing start address is overwritten,

having a display controller to which the overtake signal is fed, in which case the display controller can select, by evaluating the overtake signal, the memory segment corresponding to the last writing start address stored or the penultimate writing start address stored, for read-out by a read controller, connected to the segment buffer, with the aid of continuously incremented read addresses and for insertion into the respective main picture.

7. The circuit arrangement of claim 6 wherein the write controller and the read controller each have an address counter for incrementing the write addresses and read addresses, respectively.

8. The circuit arrangement of claim 6 wherein, by means of the display controller, an insertion position of an inset picture is calculated and a corresponding insertion signal can be fed to an insertion apparatus.

9. The circuit arrangement of claim 6 wherein, by means of the display controller, raster correction can be carried out by comparison between the raster position of a picture to be displayed and the raster position of a stored picture and also by skipping or repeating a line.

10. A circuit arrangement of claim 6 wherein provision is made of a comparator for comparing the instantaneous write address provided by an address counter with the penultimate writing start address stored, the output of the comparator being connected to a flip-slop for driving a multiplexer, and in that the penultimate writing start address stored is present at a first input of the multiplexer and the last writing start address stored is present at a second input of the multiplexer, with the result that, in the event of correspondence between the instantaneous write address of the address counter and the penultimate writing start address stored, the multiplexer outputs the last writing start address stored as reading start address, whereas otherwise the multiplexer outputs the penultimate writing start address stored as reading start address.