System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system

1. A system comprising:

a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith;

a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic;

a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem;

wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM;

wherein the first & second EEPROM are located on separate PC boards of the system;

wherein the processor is coupled to the common configuration logic through a third serial bus;

wherein the programmable logic devices are field programmable gate arrays; and

wherein at least one EEPROM is located on the same integrated circuit as a field programmable gate array.

2. A system comprising:

a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith;

a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic;

a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem;

network interconnect, for coupling the system to a network;

wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM;

wherein the first & second EEPROM are located on separate PC boards of the system;

wherein the processor is coupled to the common configuration logic through a third serial bus;

wherein the programmable logic devices are field programmable gate arrays;

wherein a processor of the system is capable of transferring configuration code from a configuration code database on a network server through the common configuration logic and writing the configuration code into an EEPROM of the system; and

wherein at least one of the programmable logic devices performs system management functions and couples to a system management bus.

3. A system comprising:

a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith;

a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic;

a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem;

network interconnect, for coupling the system to a network;

wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM;

wherein the first & second EEPROM are located on separate PC boards of the system;

wherein the processor is coupled to the common configuration logic through a third serial bus;

wherein the programmable logic devices are field programmable gate arrays; and

wherein the processor is coupled to the common configuration logic through a system management processor, the system management processor being coupled to the common configuration logic through the third serial bus.

4. A method of in-system programming of EEPROMs, the EEPROMS being coupled to provide configuration code to FPGAs, comprising:

transferring at least portions of a configuration code file to a system management processor of the system;

providing a system management bus coupling the system management processor to common configuration logic, the common configuration logic coupled to a plurality of serial busses coupled to a plurality of the EEPROMS;

setting selection logic to designate an active serial bus coupled to an EEPROM to be programmed;

verifying compatibility of the configuration code file with the active serial bus;

erasing at least a portion of the EEPROM to be programmed;

writing at least a portion of the configuration code file from the system management processor, over the system management bus, over the active serial bus, and into the EEPROM; and causing configuration code to be loaded from the EEPROM into at least one FPGA.

5. The method of claim 4 , wherein the configuration code is located on a drive of the system.

6. The method of claim 4 , further comprising the steps of locating the configuration code file on a server of a network, and downloading the configuration code file to the system.

7. The method of claim 6 , wherein the step of causing configuration code to be loaded from the EEPROM into at least one FPGA is performed without cycling power.

8. A method of self-repairing a system by in-system programming of EEPROMs, the EEPROMS being coupled to provide configuration code to FPGAs, comprising:

detecting an error in FPGA configuration code as the FPGA configuration code is fetched from an EEPROM;

locating an FPGA configuration code file in a database;

transferring at least portions of the configuration code file to a system management processor of the system;

providing a system management bus coupling the system management processor to common configuration logic, the common configuration logic being coupled to a plurality of serial busses coupled to a plurality of the EEPROMS;

setting selection logic to designate an active serial bus coupled to an EEPROM to be programmed;

verifying compatibility of the configuration code file with the active serial bus;

erasing at least a portion of the EEPROM to be programmed;

writing at least a portion of the configuration code file from the system management processor, over the system management bus, over the active serial bus, and into the EEPROM; and

causing configuration code to be loaded from the EEPROM into at least one FPGA.