Method and system for accessing data
View Patent ↗A system and a method for transcoding multiple media channels is disclosed herein. The system includes a first processor to parse a media data stream having one or more media data channels and a vector processor to decompress, scale, and then compress the parsed media channel. A parsed media data channel, in one embodiment, is accessed using a bit manipulator and packetized into decoder instruction packets and transmitted to the vector processor using a sequencer. The vector processor decompresses the decoder instruction packets, scales a macroblock generated from the packets, and then compresses the scaled macroblock. As a result, the scaled and compressed output has less data associated with the media channel, allowing for faster and/or more efficient storage or transmission. A reduced sized scale buffer is associated with another disclosed embodiment.
1. A video transcoding system comprising:
a general purpose data processor comprising an input data port, and an output control port disposed at a semiconductor substrate;
a video transcoder disposed at the semiconductor substrate comprising
a video decoder,
a video encoder, including a Huffman encoder, coupled to receive decoded video data from the video decoder,
a storage area to store bits of compressed video data from the Huffman encoder in a bit level manner until a predefined amount of data is ready to be stored;
a memory controller disposed at the semiconductor substrate comprising a first data port to interface with a memory external the semiconductor substrate; and a second data port coupled to the input data port of the general purpose data processor and to the video transcoder;
a memory disposed at the semiconductor substrate comprising a plurality data words, each data word having a bit size of N, where N is based on a size of at least a portion of the second data port of the memory controller, each data word further having a first bit and a last bit; and
a bit level data access controller disposed at the semiconductor substrate to access bit level data, the data access controller comprising
an input data port coupled to the second data port of the memory controller,
an input control port coupled to the output control port of the general purpose processor, and
a data shifter comprising an input port coupled to the memory, and an output port coupled to the input data port of the general purpose data processor, the data shifter to provide at its output port bit values that are shifted relative to their storage location within a data word of the plurality of data words based on a value received at the input control port.
2. The system of claim 1 , wherein the memory is dedicated to the bit level data access controller.