Data link/physical layer packet buffering and flushing
View Patent ↗A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.
1. A networking apparatus comprising:
a switching fabric including a plurality of ingress/egress points to switch routing paths of packets received through mediums coupled to the ingress/egress points;
a first buffering structure, coupled to a first one of said ingress/egress points and a first one of said mediums, including a first First In First Out (FIFO) storage structure to stage a first plurality of egress packets, and packet diversion and insertion logic to enable post-switching pre-medium diversion and insertion of egress packets on the first one of said mediums;
a second buffering structure, coupled to a second one of said ingress/egress points and a second one of said mediums, including a second FIFO storage structure to stage a second plurality of egress packets, and packet diversion and insertion logic to enable post-switching pre-medium diversion and insertion of egress packets on the second one of said mediums; and
egress packet write drop logic, which, in response to an overflow condition of said first FIFO storage structure, while operating under first protocol, writes an End of Packet (EOP) at an offset from a Start of Packet (SOP) location of an egress packet to be dropped, to effectuate a tail flush of said first FIFO storage structure.
2. The apparatus of claim 1 , wherein said egress packet write drop logic, which, in response to an overflow condition of said first FIFO storage structure while operating under a first protocol,
reloads a write pointer associated with the first FIFO storage structure to point to a location in the first FIFO storage structure that is of a predetermined offset from a location pointed to by a read pointer associated with the first FIFO storage structure, and
writes an EOP at the location being pointed to by the reloaded write pointer, to effectuate a tail flush of said first FIFO storage structure.
3. The apparatus of claim 2 , wherein said egress packet write drop logic further sets a bad egress packet bit to denote for a downstream processor that an immediately preceding egress packet was aborted, while writing an EOP at the location being pointed to by the reloaded write pointer.
4. The apparatus of claim 1 , further comprising a processor interface coupled to each of the first and the second buffering structures, to respectively enable communication between the first and the second buffering structures and a first and second processor.
5. The apparatus of claim 4 , wherein said first and second processors comprise Application Specific Integrated Circuits (ASICs).
6. The apparatus of claim 1 , wherein said diversion and insertion are performed during data link/physical layer processing of egress packets.
7. The apparatus of claim 6 , wherein said diversion and insertion and said data link/physical layer processing of egress packets are performed by a single Application Specific Integrated Circuit (ASIC).
8. The apparatus of claim 1 , further comprising egress packet read drop logic, which, in response to an underflow condition of said first FIFO storage structure, while operating under a first protocol, multiplexes an EOP into said first plurality of egress packets to denote to a downstream processor that a current egress packet is bad, to effectuate a head flush of said first FIFO storage structure.
9. A networking apparatus comprising:
a switching fabric including a plurality of ingress/egress points to switch routing paths of packets received through mediums coupled to the ingress/egress;
a first buffering structure, coupled to a first one of said ingress/egress points and a first of said mediums, including a first First In First Out (FIFO) storage structure to stage a first plurality of ingress packets, and packet diversion and insertion logic to enable post-medium extraction, pre-switching diversion and insertion of egress packets on the first one of said mediums; and
a second buffering structure, coupled to a second one of said ingress/egress points and a second of said mediums, including a second FIFO storage structure to stage a second plurality of ingress packets, and packet diversion and insertion logic to enable post-medium extraction, pre-switching diversion and insertion of egress packets on the second one of said mediums; and
ingress packet write drop logic, which, in response to an overflow condition of said third FIFO storage structure, while operating under a first protocol,
writes an End of Packet (EOP) at an offset from a Start of Packet (SOP) location of an ingress packet to be dropped, to effectuate a tail flush of said first FIFO storage structure.
10. The apparatus of claim 9 , wherein said ingress packet write drop logic, which, in response to an overflow condition of said first FIFO storage structure while operating under a first protocol,
reloads a write pointer associated with the first FIFO storage structure to point to a location in the first FIFO storage structure that is of a predetermined offset from a location pointed to by a read pointer associated with the first FIFO storage structure, and
writes an EOP at the location being pointed to by the reloaded write pointer, to effectuate a tail flush of said first FIFO storage structure.
11. The apparatus of claim 10 , wherein said ingress packet write drop logic further sets a bad ingress packet bit to denote for a system-side interface that an immediately preceding ingress packet was aborted, while writing an EOP at the location being pointed to by the reloaded write pointer.
12. The apparatus of claim 9 , further comprising a processor interface coupled to each of the first and the second buffering structures, to respectively enable communication between the first and the second buffering structures and a first and second processor.
13. The apparatus of claim 9 , wherein said first and second processors comprise Application Specific Integrated Circuits (ASICs).
14. The apparatus of claim 9 , wherein said diversion and insertion are performed during data link/physical layer processing of ingress packets.
15. The apparatus of claim 9 , further comprising ingress packet read drop logic, which, in response to an underflow condition of said first FIFO storage structure, while operating under a first protocol,
multiplexes an EOP into said first plurality of ingress packets to denote a system-side interface that a current ingress packet is bad, to effectuate a head flush of said first FIPO storage structure.
16. The apparatus of claim 9 , wherein said diversion and insertion and said data link/physical layer processing of ingress packets are performed by a single Application Specific Integrated Circuit (ASIC).
17. A networking apparatus comprising:
a switching fabric including a plurality of ingress/egress points to switch packets received through mediums coupled to the ingress/egress points; and
a buffering structure including a first First In First Out (FIFO) storage structure, coupled to a first of said ingress/egress points and a first of said mediums, to stage a first plurality of ingress packets, and packet diversion and insertion logic to enable post-medium extraction, pre-switching diversion and insertion of egress packets on the first one of said mediums, and to enable post-switching pre-medium diversion and insertion of egress packets on the first one of said mediums; and
egress packet write drop logic, which, in response to an overflow condition of said first FIFO storage structure, while operating under a first protocol,
writes an End of Packet (EOP) at an offset from a Start of Packet (SOP) location of an egress packet to be dropped, to effectuate a tail flush of said first FIFO storage structure.
18. The apparatus of claim 17 , further comprising a processor interface coupled to each of the first and the second buffering structures, to respectively enable communication between the first and the second buffering structures and a first and second processor.
19. The apparatus of claim 17 , wherein said diversion and insertion are performed during data link/physical layer processing of egress packets.
20. The apparatus of claim 19 , wherein said diversion and insertion and said data link/physical layer processing of egress packets are performed by a single Application Specific Integrated Circuit (ASIC).
21. The apparatus of claim 17 , wherein said diversion and insertion are performed during data link/physical layer processing of ingress packets.
22. The apparatus of claim 17 , wherein said diversion and insertion and said data link/physical layer processing of ingress packets are performed by a single Application Specific Integrated Circuit (ASIC).