Granted Patent
Utility
US 6,512,699
· Confirmation No. 7145
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHIAL BIT LINE STRUCTURE
Inventor:
Junichi Ogane
|
⬇ PDF
|
Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-08-06 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-08-06 | A.PE |
Preliminary Amendment | 37 | View | |
| 2001-08-06 | SPEC |
Specification | 13 | View | |
| 2001-08-06 | CLM |
Claims | 4 | View | |
| 2001-08-06 | ABST |
Abstract | 1 | View | |
| 2001-08-06 | DRW |
Drawings-only black and white line drawings | 7 | View | |
| 2001-08-06 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Junichi Ogane
Tokyo, JAPAN
Classification
USPC
365/185.26
Prosecution
- Examiner
- LE, THONG QUOC
- Art Unit
- 2818
- Docket No.
- 32014-174004
- Confirmation No.
- 7145
Foreign Priority
244534/1999
·
1999-08-31
·
JAPAN
Publication
- Pub. No.
- US20020015329A1
- Pub. Date
- 2002-02-07
Patent Term Adjustment
0days
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
- Patent No.
- US 6,512,699
- App. No.
- 09/921,871
- Filed
- 2001-08-06
- Granted
- 2003-01-28
- Pub. No.
- US20020015329A1
- Examiner
- LE, THONG QUOC
- Art Unit
- 2818
- PTA
- 0 days
External Links