Method for testing integrated circuits with memory element access
View Patent ↗A method for testing an integrated circuit having memory elements which are written and/or read via an access path to the memory elements from a terminal external to the circuit. A boundary scan chain is activated to impose and/or observe logic levels on the integrated circuit inputs/outputs.
1. Process for testing an integrated circuit comprising memory points and a Boundary Scan chain, in which one writes and/or reads to and/or from the memory points by way of an access path to the memory points from an outside terminal of the circuit, comprising:
activating the Boundary Scan chain so as to impose and/or observe logic levels on the inputs/outputs of the integrated circuit.
2. Process according to claim 1 , characterized in that the access path to the memory points and the Boundary Scan chain are activated simultaneously.
3. Process according to claim 1 or 2 , characterized in that the access path to the memory points and the Boundary Scan chain are activated by way of a line comprising in series the access path to the memory points and the Boundary Scan chain.
4. Process according to claim 1 or claim 2 , characterized in that the Boundary Scan chain is activated by way of an activation path linked to the Boundary Scan chain downstream of a TAP controller.
5. Process according to claim 4 , characterized in that the activation path is linked to the Boundary Scan chain at least by a logic gate able to link, as a function of a control signal (ATPG-mode), the Boundary Scan chain or else to the activation path of the Boundary Scan, or else to the TAP controller.
6. Process according to claim 4 , characterized in that the activation path includes at least one channel (ATPG-Si) on which is placed at least one memory point, this channel being able to be linked in series with the Boundary Scan chain when the latter is activated.
7. Process according to claim 1 or claim 2 , characterized in that the input channel (Si), clock channel (ck) and configuration channel (Sh) of the Boundary Scan chain are linked to logic gates which are able to link, according to a control signal (ATPG-mode), these channels (Si, ck, Sh) or else to the input channel (Si), clock channel (ck) and configuration channel (Sh) of the TAP controller or else to the input channel (Si), clock channel (ck) and configuration channel (Sh) of the activation path.
8. Process according to claim 1 or claim 2 , characterized in that all the memory points are linked in series.
9. Process according to claim 1 or claim 2 , characterized in that at least some of the inputs/outputs of the integrated circuit are connected directly to a tester able to inject chosen signals directly into certain of these inputs/outputs, and/or to receive output signals directly from certain of these inputs/outputs and to compare these output signals with expected signals.
10. Process according to claim 1 , claim 2 or claim 9 , characterized in that the injection and/or direct measurement tester is coordinated with a device for controlling the Boundary Scan chin so as to generate test vectors on sets comprising both inputs/outputs connected directly to the tester and also inputs/outputs connected to the tester via the Boundary Scan chain.
11. Process according to claim 1 or claim 2 , characterized in that the circuit comprises accesses to its set of memory points and in that the test is carried out by controlling the set of memory points so that the function of the integrated circuit is reduced to a combinatorial function.
12. Integrated circuit comprising a Boundary Scan chain and an access path to at least one memory point, characterized in that the access path and the Boundary Scan chain are linked in series and in that the circuit comprises means for intervening simultaneously on the memory point or points of the access path and on the cells of the Boundary Scan chain.
13. Integrated circuit according to claim 12 , characterized in that the means for intervening simultaneously on the memory point or points of the access path and on the cells of the Boundary Scan chain comprise at least one logic gate able to link the Boundary Scan chain or else to the access path, or else to a TAP controller.
14. Integrated circuit according to claim 12 or claim 13 , characterized in that the input channel (SI), clock channel)(CK) and configuration channel (SHIFT) of the Boundary Scan chain are linked to logic gates which are able to link, according to a control signal (MODE), these channels or else to the input channel (SI), clock channel (CK) and configuration channel (SHIFT) of the TAP controller, or else to the input channel (ATPG_si), clock channel (ATPG_ck) and configuration channel (ATPQ_se) of the access path.
15. Integrated circuit according to claim 12 or claim 13 , characterized in that all the memory points of the integrated circuit are linked in series.
16. Integrated circuit tester, comprising:
a first module means for imposing and/or reading states of memory points of an integrated circuit,
a second module means for imposing states and/or reading states of input/output cells by way of the Boundary Scan chain of the circuit simultaneously with the action of the first module.
17. Integrated circuit tester according to claim 16 , comprising means for simultaneously injecting into an integrated circuit, control signals (SI) for the memory points and control signals (SI) for the inputs/outputs of the Boundary Scan.
18. Tester according to claim 16 , comprising means for injecting the control signals for the memory points and the control signals for the inputs/outputs of the Boundary Scan onto one and the same channel.
19. Tester according to any one of claim 16 to 18 , comprising:
a series of channels coupled directly to inputs/outputs of an integrated circuit, and
a module means for injecting chosen signals directly into certain of the inputs/outputs, and/or to receive output signals from the inputs/outputs so as to compare the output signals with expected signals.
20. Tester according to claim 19 , comprising:
a control device for the Boundary Scan chain of an integrated circuit coordinated with the direct injection/reception module so as to generate test vectors on sets comprising both inputs/outputs connected directly to the tester and also inputs/outputs connected to the tester via the Boundary Scan chain.
21. Tester according to one of claims 16 to 18 , comprising means for controlling the set of memory points in such a way that the function of the integrated circuit is reduced to a combinatorial function during the test.