IP Library Granted Patent US 6,888,877
Granted Patent B2
US 6,888,877 · App. 09/936,771 · Granted May 3, 2005

CDMA receiver

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,888,877
App. No.
09/936,771
Granted
May 3, 2005
Kind
B2
Abstract

CDMA Receiver. According to one embodiment, a CDMA receiver is provided for receiving a CDMA signal in a multi-subscriber environment. The multi-subscriber environment can include a receiving device for receiving the CDMA signal. Further, the environment can include a Rake receiving circuit for detection of signal components of the CDMA signal which are transmitted via the various signal paths. The environment can also include a channel estimation circuit for estimating channel coefficients of a transmission channel coefficient h of a transmission channel H by means of a predetermined reference data sequence contained in the received CDMA signal. A weighting coefficient calculation device can calculate weighting coefficients for the various signal components of the CDMA signal. Further, the environment can include a weighting circuit for weighting the signal components with the calculaed weighting coefficients. A combiner can combine the weighted signal components to form an estimated received data signal.

Claims (17)

1. CDMA receiver for receiving a CDMA signal, which is transmitted at a chip clock rate from a transmitter via various signal paths of a physical transmission channel, in a multi-subscriber environment having:

(a) a receiving device for receiving the CDMA signal;

(b) a Rake receiving circuit having a number of parallel-connected delay devices for detection of signal components of the CDMA signal which are transmitted via the various signal paths;

(c) a channel estimation circuit for estimating channel coefficients h of a transmission channel H by means of a predetermined reference data sequence which is contained in the received CDMA signal;

(d) a weighting coefficient calculation device for calculating weighting coefficients m for the various signal components of the CDMA signal as a function of the estimated channel coefficients h and of stored spreading and scrambling codes;

(e) a weighting circuit for weighting the signal components with the calculated weighting coefficients m; and having

(f) a combiner for combining the weighted signal components to form an estimated received data signal.

2. CDMA receiving according to claim 1 , wherein the weighting coefficient calculation device is connected to a memory device.

3. CDMA receiving according to claim 1 , wherein spreading codes C sp of the subscriber and scrambling codes C sc from the transmitter are stored in a memory device.

4. CDMA receiver according to claim 1 , wherein the combiner is an adder for adding the weighted signal components.

5. CDMA receiver according to claim 1 , wherein the reference data sequence is processed by the channel estimation circuit at the chip clock rate T c .

6. CDMA receiving according to claim 1 , wherein the delay devices of the Rake receiving circuit delay the received CDMA signal by an associated time delay T differing by precisely one chip clock cycle T C between the various delay devices.

7. CDMA receiver according to claim 1 , wherein an output circuit is provided for outputting the reference data sequence from the received CDMA received signal.

8. CDMA receiver according to claim 1 , wherein the weighting circuit comprises a large number of multiplication circuits, which are each followed by a delay device.

9. CDMA receiver according to claim 1 , wherein the channel estimation circuit is a DSP processor.

10. CDMA receiver according to claim 1 , wherein the weighting coefficient calculation device is a DSP processor.

11. CDMA receiver according to claim 2 , wherein the memory device is an RAM memory.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →