Granted Patent
Utility
US 6,476,505
· Confirmation No. 7092
SEMICONDUCTOR DEVICE HAVING PADS, THE INTERVALS OF WHICH ARE ADJUSTED AND ARRANGED IN SEMICONDUCTOR CHIP CORNERS
Inventor:
Akio Nakamura
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-08-30 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-08-30 | A.PE |
Preliminary Amendment | 2 | View | |
| 2001-08-30 | SPEC |
Specification | 18 | View | |
| 2001-08-30 | CLM |
Claims | 6 | View | |
| 2001-08-30 | ABST |
Abstract | 1 | View | |
| 2001-08-30 | DRW |
Drawings-only black and white line drawings | 15 | View | |
| 2001-08-30 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Akio Nakamura
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
257/786
H10W20/43
H10W72/071
H10W72/983
H10W72/536
H10W72/07554
H10W72/5363
H10W72/932
H10W72/9445
H10W72/951
H10W72/075
H10W90/756
H10W72/547
H10W90/754
H10W72/5522
H10W72/926
H10W72/59
H10W70/60
H10W72/5449
H10W72/934
Prosecution
- Examiner
- THAI, DAVIS
- Art Unit
- 2827
- Customer No.
- 23995
- Docket No.
- OKI 243 D1
- Confirmation No.
- 7092
Foreign Priority
119732/99
·
1999-04-27
·
JAPAN
Publication
- Pub. No.
- US20020024149A1
- Pub. Date
- 2002-02-28
Patent Term Adjustment
0days
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Quick Facts
- Patent No.
- US 6,476,505
- App. No.
- 09/941,583
- Filed
- 2001-08-30
- Granted
- 2002-11-05
- Pub. No.
- US20020024149A1
- Examiner
- THAI, DAVIS
- Art Unit
- 2827
- PTA
- 0 days
External Links