IP Library Granted Patent US 6,959,060
Granted Patent B2
US 6,959,060 · App. 09/942,638 · Granted Oct 25, 2005

Jitter reducing apparatus using digital modulation technique

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Quick Facts
Patent No.
US 6,959,060
App. No.
09/942,638
Granted
Oct 25, 2005
Kind
B2
Abstract

A jitter reducing apparatus using a digital modulation technique includes: an elastic store storing data flowed in from an SDH network; a pattern generator controlling a data read speed so the elastic store maintains a constant data storing amount; a modulation sequencer generating a digital signal wave having a constant period and amplitude; and a phase level detector controlling the pattern generator using the digital signal wave of the modulation sequencer.

Claims (30)

1. A jitter reducing apparatus, comprising:

an elastic store that stores data received from a synchronous digital hierarchy (SDH) network;

a pattern generator that controls a data read speed so the elastic store maintains a constant amount of stored data;

a modulation sequencer that outputs signals representative of a digital signal wave having a constant period and amplitude, wherein the output signals include a signal indicative of an amplitude of the digital signal wave and a signal indicative of a direction of the digital signal wave; and

a phase level detector that controls the pattern generator based on the signals output from the modulation sequencer.

2. The apparatus of claim 1 , wherein the phase level detector further controls the pattern generator using a difference value between the amount of stored data in the elastic store and an amount of data outputted from the elastic store.

3. The apparatus of claim 1 , wherein the phase level detector is operated at time intervals upon receipt of the signals from the modulation sequencer.

4. The apparatus of claim 1 , wherein the pattern generator performs a controlling operation of a pattern generation speed at regular time intervals.

5. The apparatus of claim 1 , wherein the modulation sequencer is operated upon receipt of an 8 KHz frame pulse and a 6.48 MHz clock frequency.

6. The apparatus of claim 5 , wherein the modulation sequencer generates the digital signal wave of which one period is 16 sections of the frame pulse and has a 500 Hz bandwidth.

7. The apparatus of claim 1 , wherein the modulation sequencer outputs a mode-value signal indicative of an amplitude level of the digital signal wave and a mode-slope signal indicative of a positive and a negative direction of the digital signal wave.

8. The apparatus of claim 7 , wherein the mode-slope signal controls a positive section or a negative section of the digital signal wave.

9. The apparatus of claim 7 , wherein the mode-value signal comprises one of four signal values of 00, 01, 10, and 11.

10. The apparatus of claim 7 , wherein the mode-value signal and the mode-slope signal implement a binary code signal with a high voltage level and a low voltage level.

11. An apparatus comprising:

an elastic store device to store data;

a pattern generator to control a data read speed from the elastic store device so as to maintain an approximately constant amount of stored data;

a phase level device to control the pattern generator; and

a modulation sequencer to output signals representative of a digital signal wave to the phase level device, the output signals including at least an amplitude signal and a slope signal.

12. The apparatus of claim 11 , wherein the phase level device controls the pattern generator based on the signals output from the modulation sequencer and a difference between the amount of stored data in the elastic store and an amount of data outputted from the elastic store device.

13. The apparatus of claim 11 , wherein the elastic store device stores data received from a synchronous digital hierarchy network.

14. The apparatus of claim 11 , wherein the modulation sequencer outputs a mode-value signal indicative of an amplitude level of the digital signal wave and a mode-slope signal indicative of a positive direction or a negative direction of the digital signal wave.

15. The apparatus of claim 14 , wherein the mode-slope signal controls a positive section or a negative section of the digital signal wave.

16. The apparatus of claim 14 , wherein the mode-value signal comprises one of four signal values of 00, 01, 10 and 11.

17. The apparatus of claim 14 , wherein the mode-value signal and the mode-slope signal implement a binary code signal with a high voltage level and a low voltage level.

18. An apparatus comprising:

an elastic store device to store data;

a modulation sequencer device to output signals representative of a digital signal; and

a device to receive the signals output from the modulation sequencer device and to control a data read speed from the elastic store device, wherein the signals output from the modulation sequencer device include signals indicative of a slope of a digital signal or an amplitude of the digital signal, wherein the modulation sequence device outputs a mode-value signal indicative of an amplitude level of the digital signal and a mode-slope signal indicative of a positive direction or a negative direction of the digital signal.

19. The apparatus of claim 18 , wherein the mode-slope signal controls a positive section or a negative section of the digital signal.

Assignments (3)
CHANGE OF NAME Recorded Feb 24, 2011
From: LG-NORTEL CO., LTD.
To: LG-ERICSSON CO., LTD.
Reel/Frame 025948/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2006
From: LG ELECTRONICS INC.
To: LG NORTEL CO., LTD.
Reel/Frame 018296/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2001
From: JUNG, WOON JIN
To: LG ELECTRONICS INC.
Reel/Frame 012141/0056 →