High performance equalizer with enhanced DFE having reduced complexity
View Patent ↗An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L 1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L 1 symbols (where L 1 <=L), and therefore the overall complexity of the equalizer is significantly reduced.
1. A reduced-complexity equalizer apparatus for use with communication systems requiring equalization of a received signal subject to intersymbol interference (ISI), the apparatus comprising:
a channel estimator for providing an estimated channel response of a channel from received signal data;
a device for determining if the channel is minimum phase or maximum phase;
a first decision feedback equalizer device which utilizes coefficients derived from the estimated channel response, based upon whether the channel is minimum phase or maximum phase and forms tentative symbol decisions, wherein the first decision feedback equalizer device includes a feed-forward filter and a feedback filter;
at least a second decision feedback equalizer device which utilizes coefficients derived from the estimated channel response, based upon whether the channel is minimum phase or maximum phase, and the tentative symbol decisions from the first decision feedback equalizer, to truncate the channel response to a desired channel memory, wherein at least one second decision feedback equalizer device includes a feedback filter, wherein the coefficients of the feedback filter of the second decision feedback equalizer device is a subset of those of the feedback filter of the first-decision feedback equalizer device; and
at least one non-linear equalizer device for providing equalization of the truncated channel response over the desired memory; and
whereby the overall complexity of the equalizer apparatus is reduced by reducing the effective delay spread of the channel.
2. The reduced-complexity equalizer apparatus of claim 1 , wherein post-cursor interference is subtracted from the output of the feed-forward filter in the first-decision feedback equalizer device and a hard symbol decision is made on this output.
3. The reduced-complexity equalizer apparatus of claim 1 , wherein the second-decision feedback equalizer device constructs partial post-cursor interference using the decision from the output of the first decision feedback equalizer, and subtracts the partial post-cursor interference from the output of the feed-forward filter.