Multi-master bus architecture for system-on-chip designs
View Patent ↗A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves. The system includes a plurality of multiplexers in communication with each data in port of each bus master and each bus slave. The system also includes a plurality of isolated data paths connecting the port out of each bus master to each multiplexer in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design. In addition a distributed arbitration is included to allow each bus slave to be selected independently of the other bus slaves.
1. A bus architecture system on an integrated circuit comprising:
a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave;
a plurality of multiplexers in communication with each data in port;
a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design;
an arbiter in communication with each multiplexer that is in communication with a data in port corresponding to a bus slave; and
an address decoder in communication with each multiplexer that is in communication with a data in port corresponding to a bus master.
2. The bus architecture system of claim 1 further comprising at least one of the following protocols: retry condition, data pre-fetch, address and data error recovery, or maximum latency timers.
3. The bus architecture system of claim 1 , wherein one or more of the bus masters are off chip.
4. The bus architecture system of claim 1 , wherein one or more of the bus slaves are off chip.
5. A bus architecture system on an integrated circuit comprising: a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave; a plurality of multiplexers in communication with each data in port; a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design; and an address decoder in communication with each multiplexer that is in communication with a data in port corresponding to a bus master.
6. The bus architecture system of claim 5 further comprising: an arbiter in communication with each multiplexer that is in communication with a data in port corresponding to a bus slave.
7. The bus architecture system of claim 1 or 6 further comprising a single clock controlling the bus architecture system to yield data burst rates greater than 1.6 Gbytes/s per point-to-point connection.
8. The bus architecture system of claim 1 or 6 further comprising a single clock controlling the bus architecture system to yield aggregate data burst rates greater than 10 Gbytes/s per point-to-point connection.