System and method for analyzing and optimizing computer system performance utilizing observed time performance measures
View Patent ↗A data processing system and method analyze the performance of its components by obtaining measures of usage of the components over time as well as electrical requirements of those components to recommend an optimal configuration. The location in the system and the time duration that any one or more components is in a performance-limiting or bottleneck condition is determined. Based on the observed bottlenecks, their times of occurrence and their time duration, more optimal configurations of the system are recommended. The present invention is particularly adapted for use in data processing systems where a peripheral component interconnect (PCI) bus is used.
1. A method comprising:
monitoring a first performance level of a first hardware component coupled to a first bus segment in a computer;
monitoring a second performance level of a second hardware component coupled to the first bus segment in the computer; and
in response to either the first or second hardware components exceeding a pre-determined utilization level due to an incompatibility between the first and second hardware components, dynamically reconfiguring the computer such that the second hardware component is physically de-coupled from the first bus segment, and wherein the second hardware component is subsequently physically coupled to a second bus segment that is electrically isolated from the first bus segment.
2. The method of claim 1 , wherein the pre-determined utilization level is 75% of a maximum operating capability of a hardware component being evaluated.
3. The method of claim 2 , wherein an evaluated component must exceed 75% of the maximum operating capability for at least two hours to exceed the pre-determined utilization level.
4. The method of claim 3 , wherein the first hardware component is a disk adapter.
5. The method of claim 3 , wherein the first hardware component is a Local Area Network (LAN) adapter.
6. The method of claim 3 , wherein the first hardware component is a memory chip.
7. The method of claim 3 , further comprising:
monitoring a third performance level of a third hardware component coupled to a third bus segment in the computer;
monitoring a fourth performance level of a fourth hardware component coupled to the third bus segment in the computer;
summing a first total amount of time during a two-hour window that the third and fourth hardware components each exceed the pre-determined utilization level; and
summing a second total amount of time during a two-hour window that the first and second hardware components each exceed the pre-determined utilization level; and
in response to the first total amount of time being more than the second total amount of time, skipping the step of physically de-coupling the second hardware component from the first bus segment and physically moving the fourth hardware component from the third bus segment to either the first bus segment, that is electrically isolated from the third bus segment, or the second bus segment, that is electrically isolated from the third bus segment.
8. The method of claim 3 , further comprising:
waiting at least two hours before reconfiguring the computer in accordance with the steps described in claim 1 .
9. The method of claim 1 , wherein the first and second bus segments are secondary Peripheral Computer Interconnect (PCI) busses that are coupled to a primary PCI bus.
10. The method of claim 9 , wherein each secondary PCI bus is coupled to a same primary PCI bus via a different PCI-to-PCI bridge.
11. The method of claim 1 , wherein the incompatibility between the first and second hardware components is due to a difference in data throughput speeds in the first and second hardware components.
12. A computer program product, residing on a computer usable medium, comprising:
computer program code for monitoring a first performance level of a first hardware component coupled to a first bus segment in a computer;
computer program code for monitoring a second performance level of a second hardware component coupled to the first bus segment in the computer; and
computer program code for, in response to either the first or second hardware components exceeding a pre-determined utilization level due to an incompatibility between the first and second hardware components, dynamically reconfiguring the computer such that the second hardware component is physically de-coupled from the first bus segment, and wherein the second hardware component is subsequently physically coupled to a second bus segment that is electrically isolated from the first bus segment.
13. The computer program product of claim 12 , wherein the pre-determined utilization level is 75% of a maximum operating capability of a hardware component being evaluated.
14. The computer program product of claim 13 , wherein an evaluated component must exceed 75% of the maximum operating capability for at least two hours to exceed the pre-determined utilization level.
15. The computer program product of claim 14 , further comprising:
computer program code for monitoring a third performance level of a third hardware component coupled to a third bus segment in the computer;
computer program code for monitoring a fourth performance level of a fourth hardware component coupled to the third bus segment in the computer;
computer program code for summing a first total amount of time during a two-hour window that the third and fourth hardware components each exceed the pre-determined utilization level;
computer program code for summing a second total amount of time during a two-hour window that the first and second hardware components each exceed the pre-determined utilization level; and
computer program code for, in response to the first total amount of time being more than the second total amount of time, skipping the step of physically do-coupling the second hardware component from the first bus segment and physically moving the fourth hardware component from the third bus segment to either the first bus segment, that is electrically isolated from the third bus segment, or the second bus segment, that is electrically isolated from the third bus segment.
16. The computer program product of claim 14 , further comprising:
computer program code for waiting at least two hours before reconfiguring the computer in accordance with the steps described in claim 1 .
17. The computer program product of claim 13 , wherein the first hardware component is a memory chip.
18. The computer program product of claim 12 , wherein the first and second bus segments are secondary Peripheral Computer Interconnect (PCI) busses that are coupled to a primary PCI bus.
19. The computer program product of claim 18 , wherein each secondary PCI bus is coupled to a same primary PCI bus via a different PCI-to-PCI bridge.
20. The computer program product of claim 12 , wherein the incompatibility between the first and second hardware components is duo to a difference in data throughput speeds in the first and second hardware components.