Granted Patent
Utility
US 6,506,647
· Confirmation No. 5206
METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
⬇ PDF
|
Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-09-24 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-09-24 | SPEC |
Specification | 49 | View | |
| 2001-09-24 | CLM |
Claims | 14 | View | |
| 2001-09-24 | ABST |
Abstract | 1 | View | |
| 2001-09-24 | DRW |
Drawings-only black and white line drawings | 18 | View | |
| 2001-09-24 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Kenichi Kuroda
Tachikawa, JAPAN
Kozo Watanabe
Kokubunji, JAPAN
Attorneys & Agents of Record
Classification
USPC
438/275
H10B12/09
H10D84/038
H10W20/0698
H10B12/05
H10D84/0174
H10D84/017
H10D64/664
H10W20/069
Prosecution
- Examiner
- LE, THAO P
- Art Unit
- 2818
- Customer No.
- 38327
- Docket No.
- HITA.0107
- Confirmation No.
- 5206
Foreign Priority
2000-310256
·
2000-10-11
·
JAPAN
Publication
- Pub. No.
- US20020042172A1
- Pub. Date
- 2002-04-11
Patent Term Adjustment
0days
CHANGE OF ADDRESS
Recorded 2017-11-29
from
HITACHI, LTD.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-25
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-09-24
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
- Patent No.
- US 6,506,647
- App. No.
- 09/961,059
- Filed
- 2001-09-24
- Granted
- 2003-01-14
- Pub. No.
- US20020042172A1
- Examiner
- LE, THAO P
- Art Unit
- 2818
- PTA
- 0 days
External Links