Method for implementing an efficient and economical cathode process
View Patent ↗The present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. In one embodiment, a novel etchant gas chemistry dispenses with needing a second passivation layer. In one embodiment, a direct via is formed without a separate mask. In one embodiment, access and isolation features of a metallic gate are patterned in the same patterning operation as an associated passivation layer, dispensing with a need for separate patterning of each. In one embodiment, etching is effectuated with high selectivity for nitrides of silicon. In one embodiment, the requirement for at least one passivation layer deposition, a direct via masking step, and separate patterning steps for the passivation layer and metallic gate are eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time. Advantageously, this increases efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices.
1. A method for fabricating an intermediate structure for a cathode array of a flat panel display comprising:
depositing a passivation layer of substantially nitride of silicon upon a base structure comprising an oxide of silicon inter-layer dielectric disposed upon a glass substrate, wherein said interlayer dielectric covers a first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor, said second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium;
patterning said passivation layer according to a first pattern;
in response to a determination that said passivation layer is to be etched without selectivity to nitrides of silicon with respect to oxides of silicon, further patterning said layer of chromium according to said first pattern;
in response to a determination that said passivation layer is to be etched with selectivity to nitrides of silicon with respect to oxides of silicon sufficient to avoid undesirable etching of said interlayer dielectric layer, patterning said layer of chromium according to a second pattern, wherein said second pattern is separate from said first pattern;
upon said patterning said layer of chromium according to said first pattern, etching said passivation layer using an etching technique selected from the group consisting of at least one of nitride of silicon dry etching, reactive ion etching, gaseous etching, and plasma assisted dry etching;
upon said patterning said layer of chromium according to said second pattern, etching said passivation layer using nitrides of silicon dry etching;
etching said layer of chromium; and etching said inter-layer dielectric using an inter-layer dielectric wet etch.
2. The method as recited in claim 1 , wherein said performing a nitrides of silicon dry etch comprises application of a gas mixture.
3. The method as recited in claim 2 , wherein said gas mixture comprises sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, and oxygen.
4. The method as recited in claim 2 , wherein said gas mixture comprises octafluorocyclobutane, carbon monoxide, and argon.
5. The method as recited in claim 4 , wherein said gas mixture further comprises nitrogen.
6. The method as recited in claim 1 , wherein said base structure further comprises a resistor disposed between said glass substrate and said inter-layer dielectric, and between said first metallic conductor and said inter-layer dielectric.
7. The method as recited in claim 6 , wherein said method further comprises performing a dual resistor etch.
8. The method as recited in claim 1 , wherein said first pattern comprises a template for a layout of said passivation layer.
9. The method as recited in claim 8 , wherein said first pattern further comprises a template for a layout of said layer of chromium.
10. The method as recited in claim 9 , wherein said patterning said layer of chromium according to said first pattern further comprises conforming said layout of said layer of chromium to said pattern.
11. The method as recited in claim 10 , wherein said patterning said layer of chromium according to said first pattern further comprises fixing a location for an access spot and an electrical isolation area.