IP Library Granted Patent US 7,248,658
Granted Patent B2
US 7,248,658 · App. 09/968,524 · Granted Jul 24, 2007

Method and circuit for deriving a second clock signal from a first clock signal

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Quick Facts
Patent No.
US 7,248,658
App. No.
09/968,524
Granted
Jul 24, 2007
Kind
B2
Abstract

A clock generation circuit for a dual system radio frequency station is provided. The station includes a digital synthesis circuit clocked by a first clock signal for a first RF system that is adapted to generate a base signal output of a predetermined frequency. A second clock signal is derived from the sum of the frequency of the base signal and the frequency of the first clock signal.

Claims (13)

1. A clock generation circuit for a dual communications technology system radio frequency (RF) station, including:

a digital clock synthesis circuit clocked by a first clock signal for a first communications technology RF system and adapted to generate an analog base clock signal of a predetermined frequency; and

means for deriving a second clock signal for a second communications technology RF system from an output of said digital clock synthesis circuit as a Nyquist image derived from said first clock signal.

2. A clock generation circuit for a dual communications technology system radio frequency (RF) station, including:

a digital clock synthesis circuit clocked by a first clock signal for a first communications technology RF system and adapted to generate an analog base clock signal of a predetermined frequency; and

means for deriving a Nyquist image derived from said first clock signal, said Nyquist image having the frequency of a second clack signal for a second communications technology RF system.

3. A method for deriving a second clock signal for a second communications technology system from a first clock signal of a first communications technology system, where a frequency of said second clock signal is greater than half of a frequency of said first clock signal, including:

clocking a direct digital clock synthesis circuit with said first clock signal of a first communications technology system to generate an analog base clock signal;

applying a phase step in said synthesis circuit such that a sum of a frequency of said analog base clock signal and the frequency of said first clock signal has the frequency of said second clock signal for a second communications technology system; and

deriving said second clock signal from an output of said digital clock synthesis circuit.

4. A method for deriving a second clock signal from a first clock signal according to claim 3 , wherein the frequency of said second clock signal is greater than the frequency of said first clock signal.

5. A method for deriving a second clock signal from a first clock signal according to claim 3 , wherein the frequencies of said clock signals are those used by different radio frequency communications systems.

6. A method for deriving a second clock signal from a first clock signal according to claim 3 , wherein said phase step is such that said base clock signal frequency represents a difference in frequency between said first clock signal and said second clock signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2014
From: NEC CORPORATION
To: LENOVO INNOVATIONS LIMITED (HONG KONG)
Reel/Frame 033720/0767 →