Flexible processing system
View Patent ↗A multi-mode wireless device on a single substrate includes an analog portion and a digital portion integrated on the single substrate. The analog portion includes a cellular radio core; and a short-range wireless transceiver core. The digital portion includes a multi-processor core with a master processor coupled to a router which distributes data from the radio chip to a serial-parallel array of DSP processors, each of which is connected to multiple DSP coprocessors. This arrangement allows for decoding both complex protocols at low data rates (like GPRS), simple protocols at high data rates (like 802.11A) and complex protocols at high data rates (like WCDMA), using the same hardware.
1. A portable computer system, comprising:
a processor;
a multi-mode wireless device on a single substrate coupled to the processor, the device comprising:
an analog portion integrated on the substrate, including:
a cellular radio core having an analog to digital converter (ADC) configured to receive a radio signal from an antenna, and
a short-range wireless transceiver core; and
a digital portion integrated on the substrate, including:
a reconfigurable logic core coupled to receive converted data from the ADC, the reconfigurable logic core configured to handle a plurality of wireless communication protocols;
a plurality of general-purpose processor cores coupled to the reconfigurable logic core;
a router coupled to the reconfigurable logic core, the cellular radio core, and the short-range wireless transceiver core to de-correlate data into parallel streams that are not time-correlated and to route packets of data via a first wireless transmission medium and a second wireless transmission medium; and
a memory array coupled to the reconfigurable logic core.
2. The portable computer system of claim 1 , wherein the reconfigurable logic core includes one or more digital signal processors (DSPs).
3. The portable computer system of claim 1 , wherein the reconfigurable logic core includes one or more reduced instruction set computer (RISC) processors.
4. The portable computer of claim 1 , further comprising an input recognizer embodied in a program storage device, said input recognizer configured to receive input from a user.
5. The portable computer of claim 1 , wherein the reconfigurable logic core comprises a vector processor.
6. The portable computer of claim 5 , wherein the vector processor is configured to provide a parallel data output to the plurality of general-purpose processor cores.
7. The portable computer of claim 1 , wherein the digital portion comprises a reconfigurable processor core including the reconfigurable logic core and the plurality of general-purpose processor cores.